Freescale Semiconductor, Inc.
Monitor ROM (MON)
13.4.1 Entering Monitor Mode
Table 13-1 shows the pin conditions for entering monitor mode.
Table 13-1. Mode Selection
n
P
P
P
P
Bus
Frequency
P
0
Mode
CGMOUT
Q
C
C
A
C
R
P
T
T
T
CGMXCLK
CGMVCLK
CGMOUT
--------------------------
2
(1)
1
1
0
0
1
1
1
0
Monitor
Monitor
----------------------------- or -----------------------------
VHI
2
2
CGMOUT
--------------------------
2
(1)
CGMXCLK
VHI
1. For V , see 24.5 5.0 Volt DC Electrical Characteristics and 24.2 Maximum Ratings.
HI
Enter monitor mode by either:
• Executing a software interrupt instruction (SWI), or
• Applying a logic 0 and then a logic 1 to the RST pin
Once out of reset, the MCU waits for the host to send eight security bytes
(see 13.4.7 Security). After the security bytes, the MCU sends a break
signal (10 consecutive logic 0s) to the host computer, indicating that it is
ready to receive a command.
Monitor mode uses alternate vectors for reset, SWI, and break interrupt.
The alternate vectors are in the $FE page instead of the $FF page and
allow code execution from the internal monitor firmware instead of user
code. The COP module is disabled in monitor mode as long as VHI (see
24.5 5.0 Volt DC Electrical Characteristics), is applied to either the
IRQ pin or the RST pin. See Section 9. System Integration Module
(SIM) for more information on modes of operation.
NOTE: Holding the PTC3 pin low when entering monitor mode causes a bypass
of a divide-by-two stage at the oscillator. The CGMOUT frequency is
equal to the CGMXCLK frequency, and the OSC1 input directly
generates internal bus clocks. In this case, the OSC1 signal must have
a 50 percent duty cycle at maximum bus frequency.
Technical Data
MC68HC908AS60 — Rev. 1.0
Monitor ROM (MON)
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