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MC68HC908AP64CFB 参数 Datasheet PDF下载

MC68HC908AP64CFB图片预览
型号: MC68HC908AP64CFB
PDF下载: 下载PDF文件 查看货源
内容描述: [MC68HC908AP64CFB]
分类和应用: 外围集成电路时钟
文件页数/大小: 325 页 / 1651 K
品牌: FREESCALE [ Freescale ]
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I/O Registers  
11.8.5 SCI Status Register 2  
SCI status register 2 contains flags to signal the following conditions:  
Break character detected  
Incoming data  
Address:  
$0017  
Bit 7  
6
0
5
0
4
0
3
0
2
0
1
Bit 0  
RPF  
Read:  
Write:  
Reset:  
BKF  
0
0
0
= Unimplemented  
Figure 11-14. SCI Status Register 2 (SCS2)  
BKF — Break Flag Bit  
This clearable, read-only bit is set when the SCI detects a break character on the RxD pin. In SCS1,  
the FE and SCRF bits are also set. In 9-bit character transmissions, the R8 bit in SCC3 is cleared. BKF  
does not generate a CPU interrupt request. Clear BKF by reading SCS2 with BKF set and then reading  
the SCDR. Once cleared, BKF can become set again only after logic 1s again appear on the RxD pin  
followed by another break character. Reset clears the BKF bit.  
1 = Break character detected  
0 = No break character detected  
RPF — Reception in Progress Flag Bit  
This read-only bit is set when the receiver detects a logic 0 during the RT1 time period of the start bit  
search. RPF does not generate an interrupt request. RPF is reset after the receiver detects false start  
bits (usually from noise or a baud rate mismatch) or when the receiver detects an idle character. Polling  
RPF before disabling the SCI module or entering stop mode can show whether a reception is in  
progress.  
1 = Reception in progress  
0 = No reception in progress  
11.8.6 SCI Data Register  
The SCI data register (SCDR) is the buffer between the internal data bus and the receive and transmit  
shift registers. Reset has no effect on data in the SCI data register.  
Address:  
$0018  
Bit 7  
R7  
6
5
4
3
2
1
Bit 0  
R0  
Read:  
Write:  
Reset:  
R6  
T6  
R5  
T5  
R4  
T4  
R3  
T3  
R2  
T2  
R1  
T1  
T7  
T0  
Unaffected by reset  
Figure 11-15. SCI Data Register (SCDR)  
R7/T7–R0/T0 — Receive/Transmit Data Bits  
Reading the SCDR accesses the read-only received data bits, R7–R0. Writing to the SCDR writes the  
data to be transmitted, T7–T0. Reset has no effect on the SCDR.  
NOTE  
Do not use read/modify/write instructions on the SCI data register.  
MC68HC908AP Family Data Sheet, Rev. 4  
Freescale Semiconductor  
177  
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