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MC68HC11P1CFN3 参数 Datasheet PDF下载

MC68HC11P1CFN3图片预览
型号: MC68HC11P1CFN3
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器 [Microcontrollers]
分类和应用: 微控制器
文件页数/大小: 268 页 / 2323 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
Serial Communications Interface (SCI)  
receiver wakeup requires a minimum of one idle frame time between  
messages, and no idle time between frames within a message.  
5.6.2 Address-mark wakeup  
Setting the WAKE bit in SCCR1 register enables address-mark wakeup  
mode. The address-mark wakeup method uses the MSB of each frame  
to differentiate between address information (MSB = 1) and actual  
message data (MSB = 0). All frames consist of seven information bits  
(eight bits if M bit in SCCR1 = 1) and an MSB which, when set to one,  
indicates an address frame. The first frames of each message are  
addressing frames. Receiver logic evaluates these marked frames to  
determine the receivers for which that message is intended. When a  
receiver finds that the message is not intended for it, it sets the RWU bit.  
Once set, the RWU control bit disables all but the necessary receivers  
for the remainder of the message, thus reducing software overhead for  
the remainder of that message. When the next message begins, its first  
frame will have the MSB set which will automatically clear the RWU bit  
and indicate that this is an addressing frame. This frame is always the  
first frame received after wakeup because the RWU bit is cleared before  
the stop bit for the first frame is received. This method of wakeup allows  
messages to include idle times, however, there is a loss in efficiency due  
to the extra bit time required for the address bit in each frame.  
5.7 SCI error detection  
Four error conditions can occur during SCI operation. These error  
conditions are: serial data register overrun, received bit noise, framing,  
and parity error. Four bits (OR, NF, FE, and PF) in serial  
communications status register 1 (SCSR1) indicate if one of these error  
conditions exists.  
The overrun error (OR) bit is set when the next byte is ready to be  
transferred from the receive shift register to the serial data registers  
(SCDRH/SCDRL) and the registers are already full (RDRF bit is set).  
Technical Data  
MC68HC11P2 — Rev 1.0  
Serial Communications Interface (SCI)  
For More Information On This Product,  
Go to: www.freescale.com  
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