Freescale Semiconductor, Inc.
Technical Data — MC68HC11P2
Section 11. CPU Core and Instruction Set
11.1 Contents
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
11.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
11.4 Data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
11.5 Opcodes and operands . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
11.6 Addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
11.7 Instruction set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
11.2 Introduction
This section discusses the M68HC11 central processing unit (CPU)
architecture, its addressing modes and the instruction set. For more
detailed information on the instruction set, refer to the M68HC11
Reference Manual (M68HC11RM/AD).
The CPU is designed to treat all peripheral, I/O and memory locations
identically, as addresses in the 64kbyte memory map. This is referred to
as memory-mapped I/O. There are no special instructions for I/O that are
separate from those used for memory. This architecture also allows
accessing an operand from an external memory location with no
execution-time penalty.
MC68HC11P2 — Rev 1.0
Technical Data
CPU Core and Instruction Set
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