Architecture Block Diagram
5
JTAG / EOnCE
Boot
Flash
pdb_m[15:0]
pab[20:0]
Program
Flash
Program
RAM
cdbw[31:0]
56800E
17
CHIP
TAP
Controller
Address
Data
EMI
16
6
Control
TAP
Linking
Module
Data RAM
Data Flash
xab1[23:0]
xab2[23:0]
External
JTAG
Port
cdbr_m[31:0]
xdb2_m[15:0]
To Flash
Con trol Logic
IPBus
Bridge
Flash
Memory
Module
NOT available on the 56F8166 device.
IPBus
Figure 1-1 System Bus Interfaces
Note:
Note:
Flash memories are encapsulated within the Flash Memory (FM) Module. Flash control is
accomplished by the I/O to the FM over the peripheral bus, while reads and writes are completed
between the core and the Flash memories.
The primary data RAM port is 32 bits wide. Other data ports are 16 bits.
56F8366 Technical Data, Rev. 2.0
Freescale Semiconductor
Preliminary
11
FREESCALE [ Freescale ]
