interrupt 7
mode select 7
Reset 7
R
Stop 7
TQFP
recovery from Stop state using IRQA 11, 12
RESET 7
Reset timing 7, 10
pin list by number 4
pin-out drawing (top) 1
S
Serial Host Interface 11
SHI 11
signal groupings 1
signals 1
SRAM
read and write accesses 12
write access 14
Stop state
recovery from 11, 12
Stop timing 7
supply voltage 2
T
Test Access Port timing diagram 54
Test Clock (TCLK) input timing diagram 53
thermal characteristics 2
thermal design considerations 1
Timer 18
event input restrictions 51
timing 51
Timing
Digital Audio Transmitter (DAX) 50
Enhanced Serial Audio Interface (ESAI) 48
General Purpose I/O (GPIO) Timing 45
OnCE™ (On Chip Emulator) Timing 45
Serial Host Interface (SHI) SPI Protocol Tim-
ing 37
Serial Host Interface (SHI) Timing 37
timing
DSP56367 Technical Data, Rev. 2.1
Freescale Semiconductor
Index-3
FREESCALE [ Freescale ]
