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DSP56301VF100 参数 Datasheet PDF下载

DSP56301VF100图片预览
型号: DSP56301VF100
PDF下载: 下载PDF文件 查看货源
内容描述: 24位数字信号处理器 [24-Bit Digital Signal Processor]
分类和应用: 外围集成电路数字信号处理器时钟
文件页数/大小: 124 页 / 2296 K
品牌: FREESCALE [ Freescale ]
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Power Consumption Benchmark  
M_DSR EQU $FFFFC9; DSP STATUS REGISTER (DSR)  
M_DPAR EQU $FFFFC8; DSP PCI ADDRESS REGISTER (DPAR)  
M_DPMC EQU $FFFFC7; DSP PCI MASTER CONTROL REGISTER (DPMC)  
M_DPCR EQU $FFFFC6; DSP PCI CONTROL REGISTER (DPCR)  
M_DCTR EQU $FFFFC5 ; DSP CONTROL REGISTER (DCTR)  
;
Host Control Register Bit Flags  
M_HCIE EQU 0 ; Host Command Interrupt Enable  
M_STIE EQU 1 ; Slave Transmit Interrupt Enable  
M_SRIE EQU 2 ; Slave Receive Interrupt Enable  
M_HF35 EQU $38 ; Host Flags 5-3 Mask  
M_HF3 EQU 3  
M_HF4 EQU 4  
M_HF5 EQU 5  
; Host Flag 3  
; Host Flag 4  
; Host Flag 5  
M_HINT EQU 6 ; Host Interrupt A  
M_HDSM EQU 13 ; Host Data Strobe Mode  
M_HRWP EQU 14 ; Host RD/WR Polarity  
M_HTAP EQU 15 ; Host Transfer Acknowledge Polarity  
M_HDRP EQU 16 ; Host Dma Request Polarity  
M_HRSP EQU 17 ; Host Reset Polarity  
M_HIRP EQU 18 ; Host Interrupt Request Polarity  
M_HIRC EQU 19 ; Host Interupt Request Control  
M_HM0 EQU 20 ; Host Interface Mode  
M_HM1 EQU 21 ; Host Interface Mode  
M_HM2 EQU 22 ; Host Interface Mode  
M_HM EQU $700000 ; Host Interface Mode Mask  
;
Host PCI Control Register Bit Flags  
M_PMTIE EQU 1 ; PCI Master Transmit Interrupt Enable  
M_PMRIE EQU 2 ; PCI Master Receive Interrupt Enable  
M_PMAIE EQU 4 ; PCI Master Address Interrupt Enable  
M_PPEIE EQU 5 ; PCI Parity Error Interrupt Enable  
M_PTAIE EQU 7 ; PCI Transaction Abort Interrupt Enable  
M_PTTIE EQU 9 ; PCI Transaction Termination Interrupt Enable  
M_PTCIE EQU 12  
; PCI Transfer Complete Interrupt Enable  
M_CLRT EQU 14 ; Clear Transmitter  
M_MTT EQU 15 ; Master Transfer Terminate  
M_SERF EQU 16 ; HSERR~ Force  
M_MACE EQU 18 ; Master Access Counter Enable  
M_MWSD EQU 19 ; Master Wait States Disable  
M_RBLE EQU 20 ; Receive Buffer Lock Enable  
M_IAE EQU 21 ; Insert Address Enable  
;
Host PCI Master Control Register Bit Flags  
M_ARH EQU $00ffff; DSP PCI Transaction Address (High)  
M_BL EQU $3f0000; PCI Data Burst Length  
M_FC EQU $c00000; Data Transfer Format Control  
;
Host PCI Address Register Bit Flags  
M_ARL EQU $00ffff; DSP PCI Transaction Address (Low)  
M_C EQU $0f0000; PCI Bus Command  
M_BE EQU $f00000; PCI Byte Enables  
;
DSP Status Register Bit Flags  
M_HCP EQU 0 ; Host Command pending  
DSP56301 Technical Data, Rev. 10  
A-6  
Freescale Semiconductor  
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