dc
dc
$6162BC
$E4A245
YDAT_END
;**************************************************************************
;
;
;
;
;
;
;
;
;
;
;
;
;
EQUATES for DSP56301 I/O registers and ports
Reference: DSP56301 Specifications Revision 3.00
Last update: November 15 1993
Changes:
GPIO for ports C,D and E,
HI32
DMA status reg
PLL control reg
AAR
SCI registers address
SSI registers addr. + split TSR from SSISR
December 19 1993 (cosmetic - page and opt directives)
August 9 1994 ESSI and SCI control registers bit update
;
;
;**************************************************************************
page
opt
132,55,0,0,0
mex
ioequ
ident
1,0
;------------------------------------------------------------------------
;
;
;
EQUATES for I/O Port Programming
;------------------------------------------------------------------------
;
Register Addresses
M_DATH EQU $FFFFCF ; Host port GPIO data Register
M_DIRH EQU $FFFFCE; Host port GPIO direction Register
M_PCRC EQU $FFFFBF; Port C Control Register
M_PRRC EQU $FFFFBE; Port C Direction Register
M_PDRC EQU $FFFFBD ; Port C GPIO Data Register
M_PCRD EQU $FFFFAF ; Port D Control register
M_PRRD EQU $FFFFAE ; Port D Direction Data Register
M_PDRD EQU $FFFFAD; Port D GPIO Data Register
M_PCRE EQU $FFFF9F; Port E Control register
M_PRRE EQU $FFFF9E; Port E Direction Register
M_PDRE EQU $FFFF9D; Port E Data Register
M_OGDB EQU $FFFFFC; OnCE GDB Register
;------------------------------------------------------------------------
;
;
;
EQUATES for Host Interface
;------------------------------------------------------------------------
;
Register Addresses
M_DTXS EQU $FFFFCD ; DSP SLAVE TRANSMIT DATA FIFO (DTXS)
M_DTXM EQU $FFFFCC; DSP MASTER TRANSMIT DATA FIFO (DTXM)
M_DRXR EQU $FFFFCB; DSP RECEIVE DATA FIFO (DRXR)
M_DPSR EQU $FFFFCA; DSP PCI STATUS REGISTER (DPSR)
DSP56301 Technical Data, Rev. 10
Freescale Semiconductor
A-5
FREESCALE [ Freescale ]
