In dual-address mode, two bus transfers occur, one from a source device and the other to a destination
device. Dual-address transfers can be started by either an internal or external request. In this mode, each
channel supports 32 bits of address and 8 or 16 bits of data (32 bits require external logic). The source and
destination port size can be selected independently; when they are different, the data will be packed or
unpacked. An 8-bit disk interface can be read twice before the concatenated 16-bit result is passed into
memory.
Byte, word, and long-word counts up to 32 bits can be transferred. All addresses and transfer counters are
32 bits. Addresses increment or remain constant, as programmed. The DMA channels support two external
request modes, burst transfer and cycle steal. Internal requests can be programmed to occupy 25, 50, 75, or
100 percent of the data bus bandwidth. Interrupts can be programmed to postpone DMA completion.
The DMA module can sustain a transfer rate of 12.5 Mbytes/sec in dual-address mode and nearly 50
Mbytes/sec in single-address mode @ 25.16 MHz (8.4 and 33.3 Mbytes/sec @ 16.78 MHz, respectively).
The DMA controller arbitrates with the CPU32 for the bus in parallel with existing bus cycles and is fully
synchronized with the CPU32, eliminating all delays normally associated with bus arbitration by allowing
DMA bus cycles to butt seamlessly with CPU bus cycles.
SERIAL MODULE
Most digital systems use serial I/O to communicate with host computers, operator terminals, or remote
devices. The MC68340 contains a two-channel, full-duplex USART. An on-chip baud rate generator
provides standard baud rates up to 76.8k baud independently to each channel's receiver and transmitter.
The module is functionally equivalent to the MC68681/MC2681 DUART.
Each communication channel is completely independent. Data formats can be 5, 6, 7, or 8 bits with even,
odd, or no parity and stop bits up to 2 in 1/16 increments. Four-byte receive buffers and two-byte transmit
buffers minimize CPU service calls. A wide variety of error detection and maskable interrupt capability is
provided on each channel. Full-duplex, autoecho loopback, local loopback, and remote loopback modes can
be selected. Multidrop applications are supported.
A 3.6864-MHz crystal drives the baud rate generators. Each transmit and receive channel can be
programmed for a different baud rate, or an external 1× and 16× clock input can be selected. Full modem
support is provided with separate request-to-send (RTS) and clear-to-send (CTS) signals for each channel.
One channel also provides service request signals. The two serial ports can sustain rates of 9.8 Mbps with a
25-MHz system clock in 1
×
mode, 612 kbps in 16× mode (6.5 Mbps and 410 kbps @ 16.78 MHz).
TIMER MODULES
Timers and counters are used in a system to monitor elapsed time, generate waveforms, measure signals,
keep time-of-day clocks, initiate DRAM refresh cycles, count events, and provide “time slices” to ensure that
no task dominates the activity of the processor. A counter that counts clock pulses makes a timer, which is
most useful when it causes certain actions to occur in response to reaching desired counts.
The MC68340 has two, identical, versatile, on-chip counter/timers as well as a simple timer in the SIM40.
These general-purpose counter/timers can be used for precisely timed events without the errors to which
software-based counters and timers are susceptible—e.g., errors caused by dynamic memory refreshing,
DMA cycle steals, and interrupt servicing. The programmable timer operating modes are input capture,
output compare, square-wave generation, variable duty-cycle square-wave generation, variable-width
single-shot pulse generation, event counting, period measurement, and pulse-width measurement.
Each timer consists of a 16-bit countdown counter with an 8-bit countdown prescaler for a composite 24-bit
resolution. The two timers can be externally cascaded for a maximum count width of 48 bits. The
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MC68340 PRODUCT INFORMATION
MOTOROLA
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
