Freescale Semiconductor, Inc.
SECTION 3
BUS OPERATION
This section provides a functional description of the bus, the signals that control it, and the
bus cycles provided for data transfer operations. It also describes the error and halt
conditions, bus arbitration, and reset operation. Operation of the external bus is the same
whether the MC68340 or an external device is the bus master; the names and
descriptions of bus cycles are from the viewpoint of the bus master. For exact timing
specifications, refer to Section 11 Electrical Characteristics.
The MC68340 architecture supports byte, word, and long-word operands allowing access
to 8- and 16-bit data ports through the use of asynchronous cycles controlled by the
SIZ1/SIZ0 outputs and DSACK1/DSACK0 inputs. The MC68340 requires word and long-
word operands to be located in memory on word boundaries. The only type of transfer that
can be performed to an odd address is a single-byte transfer, referred to as an odd-byte
transfer. For an 8-bit port, multiple bus cycles may be required for an operand transfer due
to either misalignment or a word or long-word operand.
3.1 BUS TRANSFER SIGNALS
The bus transfers information between the MC68340 and external memory or a peripheral
device. External devices can accept or provide 8 bits or 16 bits in parallel and must follow
the handshake protocol described in this section. The maximum number of bits accepted
or provided during a bus transfer is defined as the port width. The MC68340 contains an
address bus that specifies the address for the transfer and a data bus that transfers the
data. Control signals indicate the beginning and type of the cycle as well as the address
space and size of the transfer. The selected device then controls the length of the cycle
with the signal(s) used to terminate the cycle. Strobe signals, one for the address bus and
another for the data bus, indicate the validity of the address and provide timing information
for the data. Both asynchronous and synchronous operation is possible for any port width.
In asynchronous operation, the bus and control input signals are internally synchronized to
the MC68340 clock, introducing a delay. This delay is the time required for the MC68340
to sample an input signal, synchronize the input to the internal clocks, and determine
whether it is high or low. In synchronous mode, the bus and control input signals must be
timed to setup and hold times. Since no synchronization is needed, bus cycles can be
completed in three clock cycles in this mode. Additionally, using the fast-termination option
of the chip select signals, two-clock operation is possible.
Furthermore, for all inputs, the MC68340 latches the level of the input during a sample
window around the falling edge of the clock signal. This window is illustrated in Figure 3-1,
where t and t are the input setup and hold times, respectively. To ensure that an input
su
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signal is recognized on a specific falling edge of the clock, that input must be stable during
MOTOROLA
MC68340 USER’S MANUAL
3- 1
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