Freescale Semiconductor, Inc.
CLKOUT
FREEZE
DSCLK
DSI
SAMPLE
WINDOW
INTERNAL
SYNCHRONIZED
DSCLK
INTERNAL
SYNCHRONIZED
DSI
.
CLKOUT
Figure 5-23. Serial Interface Timing Diagram
A user can use the state change on DSO to signal hardware that the next serial transfer
may begin. A timeout of sufficient length to trap error conditions that do not change the
state of DSO should also be incorporated into the design. Hardware interlocks in the CPU
prevent result data from corrupting serial transfers in progress.
5.6.2.7.2 Development System Serial Logic. The development system, as the master of
the serial data link, must supply the serial clock. However, normal and BDM operations
could interact if the clock generator is not properly designed.
Breakpoint requests are made by asserting BKPT to the low state in either of two ways.
The primary method is to assert BKPT during a single bus cycle for which an exception is
desired. Another method is to assert BKPT, then continue to assert it until the CPU32
responds by asserting FREEZE. This method is useful for forcing a transition into BDM
when the bus is not being monitored. Each method requires a slightly different serial logic
design to avoid spurious serial clocks.
Figure 5-24 represents the timing required for asserting BKPT during a single bus cycle.
MOTOROLA
MC68340 USER’S MANUAL
5- 71
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