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BDM operation is enabled when BKPT is asserted (low) at the rising edge of RESET. BDM
remains enabled until the next system reset. A high BKPT on the trailing edge of RESET
disables BDM. BKPT is relatched on each rising transition of RESET. BKPT is
synchronized internally and must be held low for at least two clock cycles prior to negation
of RESET.
BDM enable logic must be designed with special care. If hold time on BKPT (after the
trailing edge of RESET) extends into the first bus cycle following reset, this bus cycle could
be tagged with a breakpoint. Refer to Section 3 Bus Operation for timing information.
5.6.2.2 BDM SOURCES. When BDM is enabled, any of several sources can cause the
transition from normal mode to BDM. These sources include external BKPT hardware, the
BGND instruction, a double bus fault, and internal peripheral breakpoints. If BDM is not
enabled when an exception condition occurs, the exception is processed normally. Table
5-19 summarizes the processing of each source for both enabled and disabled cases. As
depicted in the table, the BKPT instruction never causes a transition into BDM.
Table 5-19. BDM Source Summary
Source
BDM Enabled
Background
BDM Disabled
Breakpoint Exception
Halted
BKPT
Double Bus Fault
BGND Instruction
BKPT Instruction
Background
Background
Illegal Instruction
Opcode Substitution/
Illegal Instruction
Opcode Substitution/
Illegal Instruction
5.6.2.2.1 External BKPT Signal. Once enabled, BDM is initiated whenever assertion of
BKPT is acknowledged. If BDM is disabled, a breakpoint exception (vector $0C) is
acknowledged. The BKPT input has the same timing relationship to the data strobe trailing
edge as does read cycle data. There is no breakpoint acknowledge bus cycle when BDM
is entered.
5.6.2.2.2 BGND Instruction. An illegal instruction, $4AFA, is reserved for use by
development tools. The CPU32 defines $4AFA (BGND) to be a BDM entry point when
BDM is enabled. If BDM is disabled, an illegal instruction trap is acknowledged. Illegal
instruction traps are discussed in 5.5.2.8 Illegal or Unimplemented Instructions.
5.6.2.2.3 Double Bus Fault. The CPU32 normally treats a double bus fault (two bus faults
in succession) as a catastrophic system error and halts. When this condition occurs during
initial system debug (a fault in the reset logic), further debugging is impossible until the
problem is corrected. In BDM, the fault can be temporarily bypassed so that its origin can
be isolated and eliminated.
5.6.2.3 ENTERING BDM. When the processor detects a BKPT or a double bus fault or
decodes a BGND instruction, it suspends instruction execution and asserts the FREEZE
output. FREEZE assertion is the first indication that the processor has entered BDM. Once
FREEZE has been asserted, the CPU enables the serial communication hardware and
awaits a command.
5- 66
MC68340 USER’S MANUAL
MOTOROLA
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