Freescale Semiconductor, Inc.
5.1.7.1 TABLE LOOKUP AND INTERPOLATE INSTRUCTIONS. To maximize
throughput for real-time applications, reference data is often “particulated” and stored in
memory for quick access. The storage of each data point would require an inordinate
amount of memory. The table instruction requires only a sample of data points stored in
the array, thus reducing memory requirements. Intermediate values are recovered with
this instruction via linear interpolation. The results may be rounded by a round-to-nearest
algorithm.
5.1.7.2 LOW-POWER STOP INSTRUCTION. In applications where power consumption is
a consideration, the CPU32 forces the device into a low-power standby mode when
immediate processing is not required. The low-power stop mode is entered by executing
the LPSTOP instruction. The processor will remain in this mode until a user-specified (or
higher) interrupt level or reset occurs.
5.1.8 Processing States
The processor is always in one of four processing states: normal, exception, halted, or
background. The normal processing state is that associated with instruction execution; the
bus is used to fetch instructions and operands and to store results. The exception
processing state is associated with interrupts, trap instructions, tracing, and other
exception conditions. The exception may be internally generated explicitly by an
instruction or by an unusual condition arising during the execution of an instruction.
Externally, exception processing can be forced by an interrupt, a bus error, or a reset. The
halted processing state is an indication of catastrophic hardware failure. For example, if
during the exception processing of a bus error another bus error occurs, the processor
assumes that the system is unusable and halts. The background processing state is
initiated by breakpoints, execution of special instructions, or a double bus fault.
Background processing allows interactive debugging of the system via a simple serial
interface. Refer to 5.4 Processing States for details.
5.1.9 Privilege States
The processor operates at one of two levels of privilege—supervisor or user. The
supervisor level has higher privileges than the user level. Not all instructions are permitted
to execute in the lower privileged user level, but all instructions are available at the
supervisor level. This scheme allows the supervisor to protect system resources from
uncontrolled access. The processor uses the privilege level indicated by the S-bit in the
SR to select either the user or supervisor privilege level and either the user stack pointer
(USP) or SSP for stack operations.
MOTOROLA
MC68340 USER’S MANUAL
5- 7
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
