Peripheral operating requirements and behaviors
Table 14. SPI master mode timing (continued)
Nu
m.
Symbol Description
Min.
Max.
Unit
Comment
10
tRI
tFI
Rise time input
Fall time input
Rise time output
Fall time output
—
tBus - 25
ns
—
11
tRO
tFO
—
25
ns
—
1
SS
(OUTPUT)
3
2
10
10
11
11
4
SPSCK
5
=
(CPOL 0)
(OUTPUT)
5
SPSCK
(CPOL 1)
=
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
8
MSB IN
LSB IN
9
MOSI
(OUTPUT)
2
BIT 6 . . . 1
LSB OUT
MSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 13. SPI master mode timing (CPHA=0)
1
SS
(OUTPUT)
2
10
10
11
11
4
3
SPSCK
(CPOL 0)
=
(OUTPUT)
5
5
SPSCK
(CPOL 1)
=
(OUTPUT)
6
7
MISO
(INPUT)
2
MSB IN
BIT 6 . . . 1
LSB IN
9
8
MOSI
(OUTPUT)
2
PORT DATA
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
MASTER MSB OUT
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 14. SPI master mode timing (CPHA=1)
MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.
Freescale Semiconductor, Inc.
25
FREESCALE [ Freescale ]
