Freescale Semiconductor, Inc.
Multiple Serial Interface
cleared by the subsequent read of the transmit/receive data register low
byte. The transmit related bits in SCxSR1 (TDRE and TC) are cleared by
a read of the SCxSR1 register followed by a write to the transmit/receive
data registerl low byte.
Read anytime (used in auto clearing mechanism). Write has no meaning
or effect.
TDRE — Transmit Data Register Empty Flag
New data will not be transmitted unless SCxSR1 is read before writing
to the transmit data register. Reset sets this bit.
0 = SCxDR busy
1 = Any byte in the transmit data register is transferred to the serial
shift register so new data may now be written to the transmit
data register.
TC — Transmit Complete Flag
Flag is set when the transmitter is idle (no data, preamble, or break
transmission in progress). Clear by reading SCxSR1 with TC set and
then writing to SCxDR.
0 = Transmitter busy
1 = Transmitter is idle
RDRF — Receive Data Register Full Flag
Once cleared, IDLE is not set again until the RxD line has been active
and becomes idle again. RDRF is set if a received character is ready
to be read from SCxDR. Clear the RDRF flag by reading SCxSR1 with
RDRF set and then reading SCxDR.
0 = SCxDR empty
1 = SCxDR full
IDLE — Idle Line Detected Flag
Receiver idle line is detected (the receipt of a minimum of 10/11
consecutive ones). This bit will not be set by the idle line condition
when the RWU bit is set. Once cleared, IDLE will not be set again until
after RDRF has been set (after the line has been active and becomes
idle again).
0 = RxD line is idle
1 = RxD line is active
Technical Data
MC68HC912DG128 — Rev 3.0
Multiple Serial Interface
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