Freescale Semiconductor, Inc.
Enhanced Capture Timer
Bit 7
Bit 15
Bit 7
6
14
6
5
13
5
4
12
4
3
11
3
2
10
2
1
9
1
Bit 0
Bit 8
Bit 0
TC0H — Timer Input Capture Holding Register 0
$00B8–$00B9
Bit 7
Bit 15
Bit 7
6
14
6
5
13
5
4
12
4
3
11
3
2
10
2
1
9
1
Bit 0
Bit 8
Bit 0
TC1H — Timer Input Capture Holding Register 1
$00BA–$00BB
Bit 7
Bit 15
Bit 7
6
14
6
5
13
5
4
12
4
3
11
3
2
10
2
1
9
1
Bit 0
Bit 8
Bit 0
TC2H — Timer Input Capture Holding Register 2
$00BC–$00BD
Bit 7
Bit 15
Bit 7
6
14
6
5
13
5
4
12
4
3
11
3
2
10
2
1
9
1
Bit 0
Bit 8
Bit 0
TC3H — Timer Input Capture Holding Register 3
$00BE–$00BF
Read: any time
Write: has no effect.
These registers are used to latch the value of the input capture registers
TC0 – TC3. The corresponding IOSx bits in TIOS ($80) should be
cleared (see IC Channels).
Technical Data
MC68HC912DG128 — Rev 3.0
Enhanced Capture Timer
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