Freescale Semiconductor, Inc.
Enhanced Capture Timer
BIT 7
6
0
0
5
0
0
4
0
0
3
0
0
2
0
0
1
PBOVF
0
BIT 0
0
0
0
0
RESET:
PBFLG — Pulse Accumulator B Flag Register
$00B1
Read: any time
Write: any time
PBOVF — Pulse Accumulator B Overflow Flag
This bit is set when the 16-bit pulse accumulator B overflows from
$FFFF to $0000, or when 8-bit pulse accumulator 1 (PAC1) overflows
from $FF to $00.
This bit is cleared by a write to the PBFLG register with bit 1 set.
Any access to the PACN1 and PACN0 registers will clear the PBOVF
flag in this register when TFFCA bit in register TSCR($86) is set.
BIT 7
BIt 7
Bit 7
BIt 7
Bit 7
0
6
6
6
6
6
0
5
5
5
5
5
0
4
4
4
4
4
0
3
3
3
3
3
0
2
2
2
2
2
0
1
1
1
1
1
0
BIT 0
Bit 0
Bit 0
Bit 0
Bit 0
0
$00B2
$00B3
$00B4
$00B5
RESET:
PA3H
PA2H
PA1H
PA0H
PA3H–PA0H — 8-Bit Pulse Accumulators Holding Registers
$00B2–$00B5
Read: any time
Write: has no effect.
These registers are used to latch the value of the corresponding pulse
accumulator when the related bits in register ICPACR ($A8) are enabled
(see Pulse Accumulators).
Technical Data
MC68HC912DG128 — Rev 3.0
Enhanced Capture Timer
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