Freescale Semiconductor, Inc.
Enhanced Capture Timer
OC7 is still able to reset the counter if enabled while PT7 is used as input
to Pulse Accumulator.
PORTT can be read anytime. When configured as an input, a read will
return the pin level. When configured as an output, a read will return the
latched output data.
NOTE: Writes do not change pin state when the pin is configured for timer
output. The minimum pulse width for pulse accumulator input should
always be greater than the width of two module clocks due to input
synchronizer circuitry. The minimum pulse width for the input capture
should always be greater than the width of two module clocks due to
input synchronizer circuitry.
BIT 7
DDT7
0
6
DDT6
0
5
DDT5
0
4
DDT4
0
3
DDT3
0
2
DDT2
0
1
DDT1
0
BIT 0
DDT0
0
RESET:
DDRT — Data Direction Register for Timer Port
$00AF
Read or write any time.
0 = Configures the corresponding I/O pin for input only
1 = Configures the corresponding I/O pin for output.
The timer forces the I/O state to be an output for each timer port line
associated with an enabled output compare. In these cases the data
direction bits will not be changed, but have no effect on the direction
of these pins. The DDRT will revert to controlling the I/O direction of
a pin when the associated timer output compare is disabled. Input
captures do not override the DDRT settings.
Technical Data
MC68HC912DG128 — Rev 3.0
Enhanced Capture Timer
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