Freescale Semiconductor, Inc.
Flash Memory
7.3 Future Flash EEPROM Support
Design is underway to introduce an improved 5V programming Flash
EEPROM module based on SuperFlash with integrated state machine
for simplified programming and erase to be introduced on the
68HC912DG128A.
Appendix: MC68HC912DG128A Flash contains detailed information to
assist in software planning for future Flash EEPROM compatibility and
easy transition to the 68HC912DG128A.
Read operation will be fully compatible with the present Flash EEPROM
design. Write and erase algorithms will be changed along with the
functions of the bits in the control register FEECTL
It is recommended that the flash algorithm not be stored as part of the
code but loaded and executed from RAM when required. This simplifies
compatibility issues and reduces the remote possibility of Flash
corruption in the unlikely event of runaway code.
The AUTO bit in the 68HC912DG128A Flash EEPROM control register
provides support for in-circuit detection of the NVM type — attempts to
set and clear this bit will only be successful on the 68HC912DG128A
where it will read as ‘1’ or ‘0’ as appropriate, on the 68HC912DG128A it
is tied to ‘0’.
To ensure full compatibility it is recommended that all of Appendix:
MC68HC912DG128A Flash be reviewed.
7.4 Overview
The Flash EEPROM array is arranged in a 16-bit configuration and may
be read as either bytes, aligned words or misaligned words. Access time
is one bus cycle for byte and aligned word access and two bus cycles for
misaligned word operations.
The Flash EEPROM module requires an external program/erase voltage
(VFP) to program or erase the Flash EEPROM array. The external
program/erase voltage is provided to the Flash EEPROM module via an
external VFP pin. To prevent damage to the flash array, VFP should
Technical Data
MC68HC912DG128 — Rev 3.0
Flash Memory
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