Freescale Semiconductor, Inc.
Monitor Read-Only Memory (MON)
IRQ1
SEE NOTE
V
DD
4096 + 32 CGMXCLK CYCLES
RST
24 CGMXCLK CYCLES
Note: Any delay between rising IRQ1 and rising V will guarantee that the MCU bus is driven by the external clock.
DD
FROM HOST
PA0
1
1
3
1
3
2
1
256 CGMXCLK CYCLES
ONE BIT TIME
FROM MCU
Notes: 1 = Echo delay (2 bit times)
2 = Data return delay (2 bit times)
3 = Wait 1 bit time before sending next byte.
Figure 10-6. Monitor Mode Entry Timing
If the received bytes match those at locations $FFF6–$FFFD, the host
bypasses the security feature and can read all FLASH locations and
execute code from FLASH. Security remains bypassed until a power-on
reset occurs. After the host bypasses security, any reset other than a
power-on reset requires the host to send another eight bytes, but
security remains bypassed regardless of the data that the host sends.
If the received bytes do not match the data at locations $FFF6–$FFFD,
the host fails to bypass the security feature. The MCU remains in monitor
mode, but reading FLASH locations returns undefined data, and trying
to execute code from FLASH causes an illegal address reset. After the
host fails to bypass security, any reset other than a power-on reset
causes an endless loop of illegal address resets.
Advance Information
160
MC68HC908RFRK2
Monitor Read-Only Memory (MON)
MOTOROLA
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