Revision History
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision History
Date
Revision
Level
Description
Figure 2-1. MC68HC908MR32 Memory Map — Added FLASH Block Protect
Register (FLBPR) at address location $FF7E
Figure A-1. MC68HC908MR16 Memory Map — Added FLASH Block Protect
Register (FLBPR) at address location $FF7E
3.3.3 Conversion Time — Reworked equations and text for clarity.
Figure 18-8. Monitor Mode Circuit — PTA7 and connecting circuitry added
Table 18-2. Monitor Mode Signal Requirements and Options — Switch locations
added to column headings for clarity
5.0
Section 16. Timer Interface A (TIMA) — Timer discrepancies corrected throughout
this section.
Section 17. Timer Interface B (TIMB) — Timer discrepancies corrected throughout
this section.
Reformatted to meet current publication standards
2.8.2 FLASH Page Erase Operation — Procedure reworked for clarity
2.8.3 FLASH Mass Erase Operation — Procedure reworked for clarity
November,
2003
6.0
2.8.4 FLASH Program Operation — Procedure reworked for clarity
Figure 14-14. SIM Break Status Register (SBSR) — Clarified definition of SBSW bit.
19.5 DC Electrical Characteristics — Corrected maximum value for monitor mode
entry voltage (on IRQ)
19.6 FLASH Memory Characteristics — Updated table entries
July,
2005
6.1
Updated to meet Freescale identity guidelines.
Page
Number(s)
29
306
50
279
281
233
255
Throughout
42
42
43
207
291
292
Throughout
August,
2001
October,
2001
3.0
4.0
December,
2001
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
4
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
