August 27, 1998
GENERAL RELEASE SPECIFICATION
SECTION 17
INSTRUCTION SET
This section describes the addressing modes and instruction types.
17.1 ADDRESSING MODES
The CPU uses eight addressing modes for flexibility in accessing data. The
addressing modes define the manner in which the CPU finds the data required to
execute an instruction. The eight addressing modes are the following:
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•
•
•
•
•
•
•
Inherent
Immediate
Direct
Extended
Indexed, No Offset
Indexed, 8-Bit Offset
Indexed, 16-Bit Offset
Relative
17.1.1 Inherent
Inherent instructions are those that have no operand, such as return from interrupt
(RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU
registers, such as set carry flag (SEC) and increment accumulator (INCA).
Inherent instructions require no memory address and are one byte long.
17.1.2 Immediate
Immediate instructions are those that contain a value to be used in an operation
with the value in the accumulator or index register. Immediate instructions require
no memory address and are two bytes long. The opcode is the first byte, and the
immediate data value is the second byte.
MC68HC05SB7
REV 2.1
INSTRUCTION SET
MOTOROLA
17-1
FREESCALE [ Freescale ]
