Freescale Semiconductor, Inc.
April 30, 1998
GENERAL RELEASE SPECIFICATION
12.1.13 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the rst 256 bytes of memory. Port
registers, port data direction registers, timer registers, and on-chip RAM locations
are in the rst 256 b ytes of memory. The CPU can also test and branch based on
the state of any bit in any of the rst 256 memory locations. Bit manipulation
instructions use direct addressing. Table 12-4 lists these instructions.
Table 12-4. Bit Manipulation Instructions
Instruction
Mnemonic
BCLR
Clear Bit
Branch if Bit Clear
Branch if Bit Set
Set Bit
BRCLR
BRSET
BSET
12.1.14 Control Instructions
These register reference instructions control CPU operation during program
execution. Control instructions, listed in Table 12-5, use inherent addressing.
Table 12-5. Control Instructions
Instruction
Mnemonic
CLC
Clear Carry Bit
Clear Interrupt Mask
CLI
No Operation
NOP
RSP
RTI
Reset Stack Pointer
Return from Interrupt
Return from Subroutine
Set Carry Bit
RTS
SEC
SEI
Set Interrupt Mask
Stop Oscillator and Enable IRQ Pin
Software Interrupt
STOP
SWI
Transfer Accumulator to Index Register
Transfer Index Register to Accumulator
Stop CPU Clock and Enable Interrupts
TAX
TXA
WAIT
MC68HC05PL4
REV 2.0
INSTRUCTION SET
12-7
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