Freescale Semiconductor, Inc.
Inte rrup ts
4.4 Inte rrup t Proc e ssing
The CPU does the following actions to begin servicing an interrupt:
• Stores the CPU registers on the stack in the order shown in
Figure 4-1
• Sets the I bit in the condition code register to prevent further
interrupts
• Loads the program counter with the contents of the appropriate
interrupt vector locations as shown in Table 4-1
The return from interrupt (RTI) instruction causes the CPU to recover its
register contents from the stack as shown in Figure 4-1. The sequence
of events caused by an interrupt is shown in the flow chart in Figure 4-2.
$0020
$0021
(Bottom of RAM)
(Bottom of Stack)
$00BE
$00BF
$00C0
$00C1
$00C2
Unstacking
Order
n
n+1
n+2
n+3
n+4
Condition Code Register
Accumulator
5
4
3
2
1
1
2
3
4
5
Index Register
Program Counter (High Byte)
Program Counter (Low Byte)
Stacking
Order
$00FD
$00FE
$00FF
Top of Stack (RAM)
Figure 4-1. Interrupt Stacking Order
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Interrupts
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