Freescale Semiconductor, Inc.
Pa ra lle l Inp ut/ Outp ut
Table 7-4. Port C Pin Functions (28-Pin Versions Only)
Control Bits
Port C
PORTC Access
Result on
Port C
Pin(s)
(Pin or Data Register)
Port C Pins
SWPDI
(in MOR)
PDICH
PDICL
DDRCx*
Read
Pin
Write
Data
Data
Data
Pulldown
Pin
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
0
0
1
X
X
X
0
1
X
0
0
0
On
Off
Off
PCx In
PCx In
PCx In
Pin
Pin
X
0
0
1
X
X
0
X
X
X
X
X
1
0
0
0
1
Data
Pin
Data
Data
Data
Data
Data
Off
On
Off
Off
Off
PCx Out
PCx In
1
Pin
PCx In
X
X
Pin
PCx In
Data
PCx Out
* DDRC can always be read or written.
X = Don’t care
7.6 Port Tra nsitions
Glitches and temporary floating inputs can occur if the control bits
regarding each port I/O pin are not performed in the correct sequence.
• Do not use read-modify-write instructions on pulldown register A
or B.
• Avoid glitches on port pins by writing to the port data register
before changing data direction register bits from a logic zero to a
logic one.
• Avoid a floating port input by clearing its pulldown register bit
before changing its data direction register bit from a logic one to a
logic zero.
• The SWPDI bit in the MOR turns off all port pulldown devices and
disables software control of the pulldown devices. Reset has no
effect on the pulldown devices when the SWPDI bit is set.
• Two or more output pins of the same port can be connected
electrically so as to provide output currents up to the sum of the
maximum specified drive currents as defined in 15.8 DC
Electrical Characteristics (5.0 Vdc) and 15.9 DC Electrical
Characteristics (3.0 Vdc). Care must be taken to assure that all
ganged pins always maintain the same output logic value.
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Parallel Input/Output
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