Freescale Semiconductor, Inc.
List of Figures
Figure
Title
Page
10-1
10-2
10-3
10-4
Core Timer Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . .148
Core Timer Status and Control Register (CTSCR) . . . . . .149
Core Timer Counter Register (CTCR) . . . . . . . . . . . . . . . .151
COP and Security Register (COPR) . . . . . . . . . . . . . . . . .152
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
11-10
11-11
Programmable Timer Overall Block Diagram. . . . . . . . . . .157
Programmable Timer Block Diagram . . . . . . . . . . . . . . . . .158
Programmable Timer Registers (TMRH and TMRL) . . . . .159
Alternate Counter Block Diagram. . . . . . . . . . . . . . . . . . . .160
Alternate Counter Registers (ACRH and ACRL) . . . . . . . .161
Timer Input Capture Block Diagram. . . . . . . . . . . . . . . . . .162
Input Capture Registers (ICRH and ICRL). . . . . . . . . . . . .163
Timer Output Compare Block Diagram . . . . . . . . . . . . . . .164
Output Compare Registers (OCRH and OCRL). . . . . . . . .165
Timer Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . .166
Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . .168
12-1
12-2
12-3
Personality EPROM Block Diagram. . . . . . . . . . . . . . . . . .172
PEPROM Bit Select Register (PEBSR) . . . . . . . . . . . . . . .173
PEPROM Status and Control Register (PESCR). . . . . . . .174
13-1
13-2
13-3
EPROM Programming Register (EPROG). . . . . . . . . . . . .180
Mask Option Register (MOR). . . . . . . . . . . . . . . . . . . . . . .182
EPROM Security in COP Register (COP) . . . . . . . . . . . . .184
15-1
15-2
15-3
15-4
SIOP Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
Stop Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . .218
Internal Reset Timing Diagram. . . . . . . . . . . . . . . . . . . . . .219
Low-Voltage Reset Timing Diagram. . . . . . . . . . . . . . . . . .219
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
List of Figures
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