Freescale Semiconductor, Inc.
Sim p le Se ria l Inte rfa c e
9.4.2 SIOP Sta tus Re g iste r (SSR)
The SIOP status register (SSR) is located at address $000B and
contains two read-only bits. Figure 9-5 shows the position of each bit in
the register and indicates the value of each bit after reset.
$000B
Read:
Write:
Reset:
Bit 7
6
5
0
4
0
3
0
2
0
1
0
Bit 0
0
SPIF
DCOL
0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-5. SIOP Status Register (SSR)
SPIF — Serial Port Interrupt Flag
The SPIF is a read-only status bit that is set on the last rising edge of
SCK and indicates that a data transfer has been completed. It has no
effect on any future data transfers and can be ignored. The SPIF bit
can be cleared by reading the SSR followed by a read or write of the
SDR or by writing a logical one to the SPIR bit in the SCR. If the SPIF
is cleared before the last rising edge of SCK it will be set again on the
last rising edge of SCK. Reset clears the SPIF bit.
1 = Serial transfer complete, serial interrupt if the SPIE bit in SCR
is set
0 = Serial transfer in progress or serial interface idle
DCOL — Data Collision
The DCOL is a read-only status bit which indicates that an illegal
access of the SDR has occurred. The DCOL bit will be set when
reading or writing the SDR after the first falling edge of SCK and
before SPIF is set. Reading or writing the SDR during this time will
result in invalid data being transmitted or received. The DCOL bit is
cleared by reading the SSR (when the SPIF bit is set) followed by a
read or write of the SDR. If the last part of the clearing sequence is
done after another transfer has started, the DCOL bit will be set again.
Reset clears the DCOL bit.
1 = Illegal access of the SDR occurred
0 = No illegal access of the SDR detected
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Simple Serial Interface
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
