Freescale Semiconductor, Inc.
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC705JJ7/ MC68HC705JP7
Se c tion 10. Core Tim e r
10.1 Conte nts
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
10.3 Core Timer Status and Control Register (CTSCR). . . . . . . . .149
10.4 Core Timer Counter Register (CTCR) . . . . . . . . . . . . . . . . . .151
10.5 COP Watchdog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
10.2 Introd uc tion
This section describes the operation of the core timer and the COP
watchdog as shown by the block diagram in Figure 10-1.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
Core Timer
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
