Freescale Semiconductor, Inc.
MC68HC05BD7 Rev. 2.0
GENERAL RELEASE SPECIFICATION
Interrupt
Y
SCLIF
=1?
N
Y
TXIF =1?
N
Clear TXIF
Write Data
to DDTR
Clear RXIF
Read Data
from DDRR
N
Y
RXIF =1?
Clr DDC1EN
Clr SCLIEN
Clr SCLIF
Y
MATCH
=1?
Address
received
N
N
SRW =1?
Y
Write
TXAK for
Next Byte
Receive
Y
TXBE
=1?
Write Data
to DDTR
N
RTI
Figure 9-1: Software Flowchart of Slave Mode Interrupt Routine
SECTION 9: DDC12AB INTERFACE
Page 47
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