Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
MC68HC05BD7 Rev. 2.0
32 T
M = $00
M = $01
M = $0F
M = $1F
Narrow pulse possibly inserted
by the BRM
T = 1 MCU Clock Period (0.5 µs if MCU clock = 2 MHz)
PWM cycles in which narrow pulses are
inserted in an 8-cycle frame
N
4
XX1
X1X
1XX
2, 6
1, 3, 5, 7
Figure 8-2: Relationship Between 5-Bit PWM and 3-Bit BRM
8.2
Open-Drain Option Register
This PWM Open-Drain option Register contains 8 bits which are programmed to change
the output drive of individual PWM channel from channel 0 to channel 7 to be open-drain
type. This register is located at $0012
7
7PWMO
0
6
6PWMO
0
5
5PWMO
0
4
4PWMO
0
3
3PWMO
0
2
2PWMO
0
1
1PWMO
0
0
0PWMO
0
R
PWMOR
$12
W
reset
Figure 8-3: PWM Open-Drain Option Register
When any bit in this register is one, the corresponding PWM channel output becomes +5V
open-drain type. When the bit is zero, the corresponding PWM channel has push-pull
output. All eight bits are clear upon reset.
SECTION 8: PULSE WIDTH MODULATION
Page 38
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