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68HC705BD7 参数 Datasheet PDF下载

68HC705BD7图片预览
型号: 68HC705BD7
PDF下载: 下载PDF文件 查看货源
内容描述: 规范2.0版(通用版) [SPECIFICATION REV 2.0 (General Release)]
分类和应用:
文件页数/大小: 85 页 / 676 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
GENERAL RELEASE SPECIFICATION  
MC68HC05BD7 Rev. 2.0  
the interrupt service routine plus 21 cycles. Once a pulse occurs, the next pulse should not  
occur until the MCU software has exited the routine (an RTI occurs). The second  
configuration shows several interrupt line “wire-ANDed” to perform the interrupts at the  
processor. Thus, if after servicing one interrupt and the interrupt line remains low, then the  
next interrupt is recognized.  
NOTE: IRQN is located at bit 3 of the Multi-function Timer Register at $0008, and  
is cleared by reset.  
Edge-sensitive Trigger Condition  
The minimum pulse width tILIH is one  
internal bus period.  
IRQ  
tILIH  
The period tILIL should not be less than the  
number of cycles it takes to execute the  
interrupt service routine plus 21 cycles  
tILIL  
tILIH  
Level-sensitive Trigger Condition  
If after servicing an interrupt, the IRQ  
remains low, then the next interrupt is  
recognized.  
IRQ1  
Normally used with pull-up resistor for  
Wire-Ored connection  
IRQn  
IRQ  
(MCU)  
Figure 4-2: External Interrupt  
4.4.2  
VSYNC Interrupt  
The VSYNC interrupt is generated when a specific edge of VSYNC input is detected as  
described in SECTION 10. The interrupt enable bit, VSIE, for the VSYNC interrupt is  
located at bit 7 of SYNC Processor Control and Status Register (SPCSR) at $000C. The I-  
bit in the CCR must be cleared in order for the VSYNC interrupt to be enabled. This  
interrupt will vector to the interrupt service routine located at the address specified by the  
contents of $3FF8 and $3FF9. The VSYNC Interrupt Flag (VSIF) must be cleared by writing  
’0’ to it in the interrupt routine.  
4.4.3  
DDC12AB Interrupt  
The DDC12AB interrupt is generated by the DDC12AB circuit as described in SECTION 9.  
The interrupt enable bit for the DDC12AB interrupt is located at bit 6 of DDC12AB Control  
Register (DCR) at $0018. The I-bit in the CCR must be cleared in order for the DDC12AB  
interrupt to be enabled. This interrupt will vector to the interrupt service routine located at  
the address specified by the contents of $3FF6 and $3FF7.  
SECTION 4: INTERRUPTS  
Page 24  
For More Information On This Product,  
Go to: www.freescale.com