Freescale Semiconductor, Inc.
July 16, 1999
GENERAL RELEASE SPECIFICATION
SECTION 7
INPUT/OUTPUT PORTS
In the normal operating mode there are 14 usable bidirectional I/O lines arranged
as one 8-bit I/O port (Port A), and one 6-bit I/O port (Port B). The individual bits in
these ports are programmable as either inputs or outputs under software control
by the data direction registers (DDR’s). Also, if enabled by a single mask option all
Port A and Port B I/O pins may have individual software programmable pull-down
or pull-up devices. Also, PA4-PA7 and PB1-PB2 pins have high current sink capa-
bility; PA0-PA3 may function as additional IRQ interrupt input sources. Note that
both PA6 and PA7 pins have Schmitt trigger input for better noise immunity. V
IH
and V specified at 2.4V and 0.8V, respectively.
IL
The four port pins, PB2-PB5 are only available on the 20-pin version of the device.
7.1
SLOW OUTPUT FALLING-EDGE TRANSITION
7
6
0
5
4
3
2
DDRB2
0
1
DDRB1
0
0
DDRB0
0
R
DDRB
$0005
DDRB5
DDRB4
DDRB3
SLOWE
0
W
reset
0
0
0
0
Figure 7-1. Port B Data Direction Register
SLOWE - Slow Transition Enable
The slow transition feature is controlled by the SLOWE bit of DDRB (Port B
Data Direction Register).
1 = Enables the slow falling-edge output transition feature on the four I/
O lines: PA6, PA7, PB1, and PB2. If the pin is configured as an
output pin.
0 = Disables slow falling-edge output transition feature on the four I/O
lines: PA6, PA7, PB1, and PB2. Default value of SLOWE bit is
cleared.
7.2
PORT A
Port A is a 8-bit bidirectional port which shares five of its pins with the IRQ inter-
rupt system as shown in Figure 7-2. Note that both PA6 and PA7 pins have
Schmitt trigger input for better noise immunity. Only the PA6 and PA7 pins are
open-drained type with slow output transition feature.
INPUT/OUTPUT PORTS
REV 2.1
7-1
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