Freescale Semiconductor, Inc.
July 16, 1999
GENERAL RELEASE SPECIFICATION
SECTION 5
RESETS
The MCU can be reset from five sources: one external input and four internal
restart conditions.
•
•
•
•
•
Initial power up of device (power on reset)
A logic zero applied to the RESET pin (external reset)
Timeout of the COP watchdog (COP reset)
Low voltage applied to the device (LVR reset)
Fetch of an opcode from an address not in the memory map (illegal
address reset)
Figure 5-1 shows a block diagram of the reset sources and their interaction.
To Interrupt
IRQ
logic
V
DD
R
Mode
Select
LATCH
R
RESET
OSC
Data
Address
COP Watchdog
(COPR)
CPU
RST
S
To other
peripherals
Illegal Address
(ILADR)
Address
LATCH
PH2
Power-On Reset
(POR)
V
DD
Low Voltage Reset
(LVR)
Figure 5-1. Reset Block Diagram
RESETS
REV 2.1
5-1
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