Freescale Semiconductor, Inc.
Op e ra ting Mod e s
1
OSC1
t
RL
RESET
t
LIH
2
IRQ
t
4064 tcyc
ILCH
3
IRQ
INTERNAL
CLOCK
INTERNAL
ADDRESS
BUS
1FFE
1FFE
1FFE
1FFE
1FFF
RESET OR INTERRUPT
VECTOR FETCH
NOTES:
1. Represents the internal gating of the OSC1 pin
2. IRQ pin edge-sensitive mask option
3. IRQ pin level- and edge-sensitive mask option
Figure 6-2. Stop Recovery Timing Diagram
During wait mode, the I bit in the CCR is cleared to enable interrupts. All
other registers, memory, and input/output lines remain in their previous
state. The timer may be enabled to allow a periodic exit from wait mode.
6.4.4 Low-Powe r Wa it
When the wait mode is entered by executing the WAIT instruction, the
oscillator divider changes from a divide-by-5 to a divide-by-40 (additional
divide-by-8) to lower the wait current. As a result, this gives a CPU clock
rate of 256 kHz if the oscillator is running with a 10.24-MHz crystal. The
oscillator divide-by-5 or divide-by-40 option is also controlled by the
speed bit located in the miscellaneous control register ($21).
Section 14. Miscellaneous Register. When returning from wait mode
via an interrupt, the OSC rate prior to entering wait mode is restored.
General Release Specification
MC68HC05CT4 — Rev. 2.0
Operating Modes
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