Clock sources
• All pins except JTAG and RESETB pins default to be GPIO inputs
• 2 mA / 9 mA source/sink capability
• Controllable output slew rate
1.7 Block Diagrams
The 56800EX core is based on a modified dual Harvard-style architecture consisting of
three execution units operating in parallel, allowing as many as six operations per
instruction cycle. The MCU-style programming model and optimized instruction set
allow straightforward generation of efficient, compact DSP and control code. The
instruction set is also highly efficient for C compilers to enable rapid development of
optimized control applications.
The device's basic architecture appears in Figure 1 and Figure 2. Figure 1 illustrates how
the 56800EX system buses communicate with internal memories and the IPBus interface
and the internal connections among each unit of the 56800EX core. Figure 2 shows the
peripherals and control blocks connected to the IPBus bridge. See the specific device’s
Reference Manual for details.
MC56F844xx Advance Information Data Sheet, Rev. 2, 06/2012.
Freescale Semiconductor, Inc.
13
Preliminary
General Business Information
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