Clock sources
JTAG
Program Bus
Core Data Bus
EOnCE
Program/Data Flash
56800EX CPU
Up to 96KB
Program
Controller
(PC)
Address
Generation
Unit (AGU)
Data Flash
32KB
FlexRAM
4
Secondary Data Bus
Arithmetic
Logic Unit
(ALU)
Bit
Manipulation
Unit
2KB
Data/Program RAM
Up to 16KB
DMA Controller
Interrupt Controller
Crystal OSC
Power Management
Controller (PMC)
Internal 8 MHz
Watchdog (COP)
Internal 32 kHz
PLL
System Integration
Module (SIM)
Periodic Interrupt
Timer (PIT) 0, 1
CRC
Peripheral Bus
QSCI
0,1
Quad Timer eFlexPWM A
I2C
0,1
QSPI
0,1
FlexCAN
A & B
NanoEdge
Inter Module CIrnotsesrbMarodInupleutcsonnection
Inter Module Crossbar Outputs
Inter-Module
Crossbar B
AND-OR-INV
Logic
GPIO & Peripheral MUX
Inter-Module
Crossbar A
Inter Module Crossbar Outputs
Inter Module Crossbar Inputs
Package
Pins
ADC C
16bit
Comparators With
6bit DAC A,B,C,D
ADC B
12bit
DAC
12bit
ADC A
12bit
PDB
0, 1
EWM
Peripheral Bus
Figure 2. System Diagram
MC56F8455x Advance Information Data Sheet, Rev. 2, 06/2012.
Freescale Semiconductor, Inc.
15
Preliminary
General Business Information
FREESCALE [ Freescale ]
