Obtaining package dimensions
• Configuring the RESET pin to GPIO output in normal operation in a high-noise
environment may help to improve the performance of noise transient immunity.
• Add a 2.2 kΩ external pullup on the TMS pin of the JTAG port to keep EOnCE in a
restate during normal operation if JTAG converter is not present.
• During reset and after reset but before I/O initialization, all I/O pins are at tri-state.
• To eliminate PCB trace impedance effect, each ADC input should have a no less than
33 pF 10Ω RC filter.
10 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to http://www.freescale.com and perform a keyword
search for the drawing’s document number:
Drawing for package
48-pin LQFP
Document number to be used
98ASH00962A
64-pin LQFP
98ASS23234W
11 Pinout
11.1 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The SIM's GPS registers are responsible
for selecting which ALT functionality is available on most pins.
64
48
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
LQFP LQFP
1
2
1
2
GPIOD2
GPIOD4
EXTAL
XTAL
RESETB
GPIOC0
GPIOC1
GPIOC2
GPIOF8
GPIOC3
GPIOC4
GPIOA7
GPIOA6
RESETB
GPIOC0
GPIOC1
GPIOC2
GPIOF8
GPIOC3
GPIOC4
GPIOA7
GPIOA6
3
3
CLKIN0
4
4
5
5
TXD0
RXD0
TA0
TB0
XB_IN2
CMPD_O
RXD0
CLKO0
CLKIN1
6
—
6
TB1
7
CMPA_O
CMPB_O
8
7
TA1
XB_IN8
EWM_OUT_B
9
—
—
ANA7&ANC11
ANA6&ANC10
10
MC56F844xx Advance Information Data Sheet, Rev. 2, 06/2012.
Freescale Semiconductor, Inc.
61
Preliminary
General Business Information
FREESCALE [ Freescale ]
