System modules
Table 29. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
VH
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
—
—
—
—
5
13
48
mV
mV
mV
mV
10
20
30
105
148
VCMPOh
VCMPOl
tDHS
Output high
Output low
VDD – 0.5
—
—
—
50
—
V
V
0.5
Propagation delay, high-speed mode (EN=1,
PMODE=1)2
ns
tDLS
Propagation delay, low-speed mode (EN=1,
PMODE=0)
250
ns
Analog comparator initialization delay3
—
—
—
7
40
—
μs
μA
V
IDAC6b
6-bit DAC current adder (enabled)
6-bit DAC reference inputs, Vin1 and Vin2
VDDA
—
VDD
There are two reference input options selectable (via
VRSEL control bit). The reference options must fall
within this range.
INL
6-bit DAC integral non-linearity
6-bit DAC differential non-linearity
–0.5
–0.3
—
—
0.5
0.3
LSB4
LSB
DNL
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6V.
2. Signal swing is 100 mV
3. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
4. 1 LSB = Vreference/64
MC56F8458x Advance Information Data Sheet, Rev. 2, 06/2012.
Freescale Semiconductor, Inc.
49
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