General
Mode
Table 9. Current Consumption (continued)
Maximum Conditions
Typical at 3.3 V, Maximum at 3.6
Frequency
25°C
V, 105°C
1
1
IDD
IDDA
IDD
IDDA
LPSTOP
(LsSTOP)
2 MHz
• 200 kHz Device Clock from Relaxation Oscillator
(ROSC)
TBD
TBD
TBD
TBD
• ROSC in standby mode
• Regulators are in standby
• PLL disabled
• Only PITs and COP enabled; other peripheral
modules disabled and clocks gated off3
• Processor core in stop mode
VLPRUN
200 kHz
• 32 kHz Device Clock
TBD
TBD
TBD
TBD
• Clocked by a 32 kHz external clock source
• Oscillator in power down
• All ROSCs disabled
• Large regulator is in standby
• Small regulator is disabled
• PLL disabled
• Repeat NOP instructions
• All peripheral modules, except COP and EWM,
disabled and clocks gated off
• Simple loop running from platform instruction
buffer
VLPWAIT
200 kHz
• 32 kHz Device Clock
TBD
TBD
TBD
TBD
• Clocked by a 32 kHz external clock source
• Oscillator in power down
• All ROSCs disabled
• Large regulator is in standby
• Small regulator is disabled
• PLL disabled
• All peripheral modules, except COP, disabled and
clocks gated off
• Processor core in wait mode
VLPSTOP
200 kHz
• 32 kHz Device Clock
TBD
TBD
TBD
TBD
• Clocked by a 32 kHz external clock source
• Oscillator in power down
• All ROSCs disabled
• Large regulator is in standby
• Small regulator is disabled
• PLL disabled
• All peripheral modules, except COP, disabled and
clocks gated off
• Processor core in stop mode
1. No output switching, all ports configured as inputs, all inputs low, no DC loads
2. ADC power consumption at higher frequency can be found in Table 26
3. In all chip LP modes and flash memory VLP modes, the maximum frequency for flash memory operation is 500 kHz due to
the fixed frequency ratio of 1:4 between the CPU clock and the flash clock.
MC56F8458x Advance Information Data Sheet, Rev. 2, 06/2012.
30
Freescale Semiconductor, Inc.
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