4.7 Peripheral Memory Mapped Registers
On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may
be accessed with the same addressing modes used for ordinary Data memory, except all peripheral
registers should be read/written using word accesses only.
Table 4-9 summarizes base addresses for the set of peripherals on the 56F8366 and 56F8166 devices.
Peripherals are listed in order of the base address.
The following tables list all of the peripheral registers required to control or access the peripherals.
Note: Features in italics are NOT available on the 56F8166 device.
Table 4-9 Data Memory Peripheral Base Address Map Summary
Peripheral
Prefix
Base Address
Table Number
External Memory Interface
Timer A
EMI
X:$00 F020
X:$00 F040
X:$00 F080
X:$00 F0C0
X:$00 F100
X:$00 F140
X:$00 F160
X:$00 F180
X:$00 F190
X:$00 F1A0
X:$00 F200
X:$00 F240
X:$00 F270
X:$00 F280
X:$00 F290
X:$00 F2A0
X:$00 F2B0
X:$00 F2C0
X:$00 F2D0
X:$00 F2E0
X:$00 F300
X:$00 F310
X:$00 F320
X:$00 F330
X:$00 F340
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
4-23
4-24
4-25
4-26
4-27
4-28
4-29
4-30
4-31
4-32
4-33
4-34
TMRA
TMRB
TMRC
TMRD
PWMA
PWMB
DEC0
DEC1
ITCN
Timer B
Timer C
Timer D
PWM A
PWM B
Quadrature Decoder 0
Quadrature Decoder 1
ITCN
ADC A
ADCA
ADCB
ADC B
Temperature Sensor
SCI #0
TSENSOR
SCI0
SCI #1
SCI1
SPI #0
SPI0
SPI #1
SPI1
COP
COP
PLL, OSC
GPIO Port A
GPIO Port B
GPIO Port C
GPIO Port D
GPIO Port E
GPIO Port F
CLKGEN
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
GPIOF
56F8366 Technical Data, Rev. 6
50
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
