Program Map
Note: Data Flash and Program RAM are NOT available on the 56F8166 device.
Table 4-1 Chip Memory Configurations
On-Chip Memory
56F8366
56F8166
Use Restrictions
Program Flash
512KB
512KB
Erase / Program via Flash interface unit and word writes to
CDBW
Data Flash
32KB
—
Erase / Program via Flash interface unit and word writes to
CDBW. Data Flash can be read via either CDBR or XDB2, but
not by both simultaneously
Program RAM
Data RAM
4KB
32KB
32KB
—
None
32KB
32KB
None
Program Boot Flash
Erase / Program via Flash Interface unit and word to CDBW
4.2 Program Map
The operating mode control bits (MA and MB) in the Operating Mode Register (OMR) control the
Program memory map. At reset, these bits are set as indicated in Table 4-2. Table 4-4 shows the memory
map configurations that are possible at reset. After reset, the OMR MA bit can be changed and will have
an effect on the P-space memory map, as shown in Table 4-3. Changing the OMR MB bit will have no
effect.
Table 4-2 OMR MB/MA Value at Reset
OMR MB =
OMR MA =
Flash Secured
State1, 2
Chip Operating Mode
EXTBOOT Pin
0
0
0
Mode 0 – Internal Boot; EMI is configured to use 16 address lines; Flash
Memory is secured; external P-space is not allowed; the EOnCE is disabled
1
Not valid; cannot boot externally if the Flash is secured and will actually
configure to 00 state
1
1
0
1
Mode 0 – Internal Boot; EMI is configured to use 16 address lines
Mode 1 – External Boot; Flash Memory is not secured; EMI configuration is
determined by the state of the EMI_MODE pin
1. This bit is only configured at reset. If the Flash secured state changes, this will not be reflected in MB until the next reset.
2. Changing MB in software will not affect Flash memory security.
56F8366 Technical Data, Rev. 6
Freescale Semiconductor
Preliminary
41
FREESCALE [ Freescale ]
