Power Distribution and I/O Ring Implementation
•
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.
This is especially critical in systems with higher capacitive loads that could create higher transient currents
in the VDD and VSS circuits.
•
•
Take special care to minimize noise levels on the VREF, VDDA and VSSA pins
Designs that utilize the TRST pin for JTAG port or EOnCE module functionality (such as development or
debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means
to assert TRST independently of RESET. Designs that do not require debugging functionality, such as
consumer products, should tie these pins together.
•
Because the Flash memory is programmed through the JTAG/EOnCE port, the designer should provide an
interface to this port to allow in-circuit Flash programming
12.3 Power Distribution and I/O Ring Implementation
Figure 12-1 illustrates the general power control incorporated in the 56F8366/56F8166. This chip
contains two internal power regulators. One of them is powered from the V
pin and cannot
DDA_OSC_PLL
be turned off. This regulator controls power to the internal clock generation circuitry. The other regulator
is powered from the V pins and provides power to all of the internal digital logic of the core, all
DD_IO
peripherals and the internal memories. This regulator can be turned off, if an external V
voltage
DD_CORE
is externally applied to the V
pins.
CAP
In summary, the entire chip can be supplied from a single 3.3 volt supply if the large core regulator is
enabled. If the regulator is not enabled, a dual supply 3.3V/2.5V configuration can also be used.
Notes:
•
•
Flash, RAM and internal logic are powered from the core regulator output
VPP1 and VPP2 are not connected in the customer system
•
All circuitry, analog and digital, shares a common VSS bus
V
DDA_OSC_PLL
V
V
DDA_ADC
DD
V
V
V
V
V
REFH
V
CAP
REG
REFP
REG
I/O
ADC
REFMID
CORE
REFN
OSC
REFLO
V
V
SS
SSA_ADC
Figure 12-1 Power Management
56F8366 Technical Data, Rev. 6
Freescale Semiconductor
Preliminary
179
FREESCALE [ Freescale ]
