Introduction
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F8366 and 56F8166 are organized into functional groups, as detailed
in Table 2-1 and as illustrated in Figure 2-1. In Table 2-2, each table row describes the signal or signals
present on a pin.
Table 2-1 Functional Group Pin Allocations
Number of Pins in Package
Functional Group
56F8366
56F8166
Power (VDD or VDDA
)
9
9
Power Option Control
1
6
1
6
Ground (VSS or VSSA
)
Supply Capacitors1 & VPP
6
6
PLL and Clock
4
17
16
6
4
17
16
6
Address Bus
Data Bus
Bus Control
Interrupt and Program Control
Pulse Width Modulator (PWM) Ports
Serial Peripheral Interface (SPI) Port 0
Serial Peripheral Interface (SPI) Port 1
6
6
25
4
13
4
—
4
4
Quadrature Decoder Port 02
4
Quadrature Decoder Port 13
Serial Communications Interface (SCI) Ports
CAN Ports
4
—
4
2
4
—
21
1
Analog to Digital Converter (ADC) Ports
Quad Timer Module Ports
21
3
JTAG/Enhanced On-Chip Emulation (EOnCE)
Temperature Sense
5
5
1
—
5
Dedicated GPIO
—
1. If the on-chip regulator is disabled, the VCAP pins serve as 2.5V VDD_CORE power inputs
2. Alternately, can function as Quad Timer pins or GPIO
3. Pins in this section can function as Quad Timer, SPI #1, or GPIO
56F8366 Technical Data, Rev. 6
Freescale Semiconductor
Preliminary
15