56F8357/56F8157 General Description
Note:
Features in italics are NOT available in the 56F8157 device.
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Access up to 4MB of off-chip program and 32MB of
data memory
• Chip Select Logic for glueless interface to ROM and
SRAM
• 256KB of Program Flash
• 4KB of Program RAM
• 8KB of Data Flash
• 16KB of Data RAM
• 16KB Boot Flash
• Up to two 6-channel PWM modules
• Four 4-channel, 12-bit ADCs
RSTO
EMI_MODE
EXTBOOT
5
JTAG/
EOnCE
Port
OCR_DIS
V
DD
V
SS
7
6
Digital Reg
* Configuration
shown for on-chip
2.5V regulator
• Temperature Sensor
• Up to two Quadrature Decoders
• Optional on-chip regulator
• FlexCAN module
• Two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interfaces (SPIs)
• Up to four general-purpose Quad Timers
• Computer Operating Properly (COP) / Watchdog
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 76 GPIO lines
• 160-pin LQFP Package and
160MAPBGA
V
PP
2
V
CAP
4
V
DDA
2
V
SSA
RESET
6
3
4
6
3
4
4
4
5
4
4
PWM Outputs
PWMA
Analog Reg
Current Sense Inputs or
GPIOC
Fault Inputs
PWM Outputs
16-Bit
56800E Core
Low Voltage
Supervisor
Bit
Manipulation
Unit
PWMB
Current Sense Inputs or GPIOD
Fault Inputs
AD0
AD1
VREF
AD0
AD1
TEMP_SENSE
Quadrature
Decoder 0 or
Quad
Timer or /
GPIOC
Quadrature
Decoder 1 or
Quad
Timer B or
SPI1 or GPIOC
Quad
Timer C or
GPIOE
Quad
Timer D or
GPIOE
FlexCAN
Program Controller
and
Hardware Looping Unit
Address
Generation Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
ADCA
PAB
PDB
CDBR
CDBW
Memory
ADCB
Program Memory
128K x 16 Flash
2K x 16 RAM
8K x 16
Boot Flash
R/W Control
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
External
Address Bus
Switch
6
2
8
4
1
A0-5 or GPIOA8-13
A6-7 or GPIOE2-3
A8-15 or GPIOA0-7
GPIOB0-3 (A16-19)
GPIOB4 (A20,
prescaler_clock)
GPIOB5-7 (A21-23,
clk0-3**)
D0-6 or GPIOF9-15
D7-15 or GPIOF0-8
WR
RD
GPIOD0-5 or CS2-7
PS (CS0) or GPIOD8
DS (CS1) or GPIOD9
**See Table 2-2
for explanation
External Bus
Interface Unit
System Bus
Control
4
Data Memory
4K x 16 Flash
8K x 16 RAM
3
7
9
External Data
Bus Switch
4
IPBus Bridge (IPBB)
Peripheral
Device Selects
RW
Control
IPAB
IPWDB
IPRDB
Bus Control
6
2
Decoding
Peripherals
Clock
resets
PLL
4
2
SPI0 or
GPIOE
4
SCI1 or
GPIOD
2
SCI0 or
GPIOE
2
COP/
Watchdog
Interrupt
Controller
IRQA
IRQB
P
System
O
Integration
R
Module
O
Clock
S
Generator
C
XTAL
EXTAL
CLKO
CLKMODE
56F8357/56F8157 Block Diagram
56F8357 Technical Data, Rev. 15
4
Freescale Semiconductor
Preliminary
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
