Quad Timer Timing
SS
(Input)
tF
tC
tR
tCL
SCLK (CPOL = 0)
(Input)
tCH
tELG
tELD
tCL
SCLK (CPOL = 1)
(Input)
tDV
tCH
tR
tD
Slave LSB out
tDI
tA
tF
MISO
Slave MSB out
MSB in
Bits 14–1
tDV
(Output)
tDS
tDH
MOSI
(Input)
Bits 14–1
LSB in
Figure 10-12 SPI Slave Timing (CPHA = 1)
10.10 Quad Timer Timing
1, 2
Table 10-18 Timer Timing
Characteristic
Timer input period
Symbol
PIN
Min
Max
Unit
ns
See Figure
10-13
2T + 6
1T + 3
1T - 3
—
—
—
—
Timer input high / low period
Timer output period
PINHL
POUT
ns
10-13
ns
10-13
Timer output high / low period
POUTHL
0.5T - 3
ns
10-13
1. In the formulas listed, T = the clock cycle. For 60MHz operation, T = 16.67ns.
2. Parameters listed are guaranteed by design.
56F8355 Technical Data, Rev. 12
Freescale Semiconductor
Preliminary
145