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56F8355_07 参数 Datasheet PDF下载

56F8355_07图片预览
型号: 56F8355_07
PDF下载: 下载PDF文件 查看货源
内容描述: 16位数字信号控制器 [16-bit Digital Signal Controllers]
分类和应用: 控制器
文件页数/大小: 164 页 / 2280 K
品牌: FREESCALE [ Freescale ]
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Operation with Security Enabled  
7.1 Operation with Security Enabled  
Once the user has programmed the Flash with his application code, the device can be secured by  
programming the security bytes located in the FM configuration field, which occupies a portion of the FM  
array. These non-volatile bytes will keep the part secured through reset and through power-down of the  
device. Only two bytes within this field are used to enable or disable security. Refer to the Flash Memory  
section in the 56F8300 Peripheral User Manual for the state of the security bytes and the resulting state  
of security. When Flash security mode is enabled in accordance with the method described in the Flash  
Memory module specification, the device will disable the core EOnCE debug capabilities. Normal  
program execution is otherwise unaffected.  
7.2 Flash Access Blocking Mechanisms  
The 56F8355/56F8155 have several operating functional and test modes. Effective Flash security must  
address operating mode selection and anticipate modes in which the on-chip Flash can be compromised  
and read without explicit user permission. Methods to block these are outlined in the next subsections.  
7.2.1  
Forced Operating Mode Selection  
At boot time, the SIM determines in which functional modes the device will operate. These are:  
Unsecured Mode  
Secure Mode (EOnCE disabled)  
When Flash security is enabled as described in the Flash Memory module specification, the device will  
disable the EOnCE debug interface.  
7.2.2  
Disabling EOnCE Access  
On-chip Flash can be read by issuing commands across the EOnCE port, which is the debug interface for  
the 56800E core. The TRST, TCLK, TMS, TDO, and TDI pins comprise a JTAG interface onto which the  
EOnCE port functionality is mapped. When the device boots, the chip-level JTAG TAP (Test Access Port)  
is active and provides the chip’s boundary scan capability and access to the ID register.  
Proper implementation of Flash security requires that no access to the EOnCE port is provided when  
security is enabled. The 56800E core has an input which disables reading of internal memory via the  
JTAG/EOnCE. The FM sets this input at reset to a value determined by the contents of the FM security  
bytes.  
7.2.3  
Flash Lockout Recovery  
If a user inadvertently enables Flash security on the device, a built-in lockout recovery mechanism can be  
used to reenable access to the device. This mechanism completely reases all on-chip Flash, thus disabling  
Flash security. Access to this recovery mechanism is built into CodeWarrior via an instruction in memory  
configuration (.cfg) files. Add, or uncomment the following configuration command:  
56F8355 Technical Data, Rev. 12  
Freescale Semiconductor  
Preliminary  
121