Peripheral Memory Mapped Registers
Table 4-18 Quadrature Decoder 1 Registers Address Map (Continued)
(DEC1_BASE = $00 F190)
Quadrature Decoder 1 is NOT available in the 56F8145 device
Register Acronym
Address Offset
Register Description
Input Monitor Register
DEC1_IMR
$D
Table 4-19 Interrupt Control Registers Address Map
(ITCN_BASE = $00 F1A0)
Register Acronym
IPR 0
Address Offset
Register Description
Interrupt Priority Register 0
$0
$1
IPR 1
Interrupt Priority Register 1
Interrupt Priority Register 2
Interrupt Priority Register 3
Interrupt Priority Register 4
Interrupt Priority Register 5
Interrupt Priority Register 6
Interrupt Priority Register 7
Interrupt Priority Register 8
Interrupt Priority Register 9
Vector Base Address Register
Fast Interrupt Match Register 0
Fast Interrupt Vector Address Low 0 Register
Fast Interrupt Vector Address High 0 Register
Fast Interrupt Match Register 1
Fast Interrupt Vector Address Low 1 Register
Fast Interrupt Vector Address High 1 Register
IRQ Pending Register 0
IPR 2
$2
IPR 3
$3
IPR 4
$4
IPR 5
$5
IPR 6
$6
IPR 7
$7
IPR 8
$8
IPR 9
$9
VBA
$A
$B
$C
$D
$E
$F
FIM0
FIVAL0
FIVAH0
FIM1
FIVAL1
FIVAH1
IRQP 0
IRQP 1
IRQP 2
IRQP 3
IRQP 4
IRQP 5
$10
$11
$12
$13
$14
$15
$16
IRQ Pending Register 1
IRQ Pending Register 2
IRQ Pending Register 3
IRQ Pending Register 4
IRQ Pending Register 5
Reserved
ICTL
$1D
Interrupt Control Register
56F8345 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
59
FREESCALE [ Freescale ]
