Architecture Block Diagram
To/From IPBus Bridge
Interrupt
CLKGEN
Controller
(OSC / PLL)
Low-Voltage Interrupt
POR & LVI
Timer A
4
System POR
RESET
Quadrature Decoder 0
Timer D
SIM
4
COP Reset
Timer B
COP
2
4
FlexCAN
Quadrature Decoder 1
SPI1
13
PWMA
SYNC Output
13
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
GPIOF
PWMB
SYNC Output
ch3i
ch2i
2
Timer C
ch3o
ch2o
8
8
ADCB
4
SPI0
SCI0
ADCA
2
1
TEMP_SENSE
2
SCI1
Note: ADC A and ADC B use the same
voltage reference circuit with VREFH
VREFP, VREFMID, VREFN, and VREFLO
pins.
,
IPBus
NOT available on the 56F8135 device.
Figure 1-2 Peripheral Subsystem
56F8335 Technical Data, Rev. 5
Freescale Semiconductor
Preliminary
11
FREESCALE [ Freescale ]
