56F826 (FREESCALE) PDF技术资料下载 56F826 供应信息 IC Datasheet 数据表 (2/56 页)-芯三七

56F826 General Description

•

Up to 40 MIPS at 80MHz core frequency

•

One Serial Port Interface (SPI)

DSP and MCU functionality in a unified,

C-efficient architecture

One additional SPI or two optional Serial

Communication Interfaces (SCI)

•

Hardware DO and REP loops

•

One Synchronous Serial Interface (SSI)

One General Purpose Quad Timer

JTAG/OnCE™ for debugging

100-pin LQFP Package

MCU-friendly instruction set supports both DSP

and controller functions: MAC, bit manipulation

unit, 14 addressing modes

•

31.5K × 16-bit words (64KB) Program Flash

512 × 16-bit words (1KB) Program RAM

2K × 16-bit words (4KB) Data Flash

4K × 16-bit words (8KB) Data RAM

2K × 16-bit words (4KB) BootFLASH

16 dedicated and 30 shared GPIO

Time-of-Day (TOD) Timer

Up to 64K × 16-bit words each of external memory

expansion for Program and Data memory

EXTBOOT

IRQB

RESET

IRQA

V

SSIO

V

SS

V

SSA

DDIO

DD

DDA

6

3

4

Low Voltage Supervisor

JTAG/

OnCE

Port

Analog Reg

TOD

Timer

Data ALU

16 x 16 + 36 → 36-Bit MAC

Three 16-bit Input Registers

Two 36-bit Accumulators

Address

Generation

Unit

Bit

Program Controller

and

Hardware Looping Unit

Interrupt

Controller

Manipulation

Unit

Program Memory

32252 x 16 Flash

512 x 16 SRAM

PAB

PDB

Quad Timer

or

GPIO

CLKO

PLL

16-Bit

56800

Core

4

XTAL

Boot Flash

2048 x 16 Flash

Clock Gen

EXTAL

XDB2

CGDB

XAB1

XAB2

Data Memory

2048 x 16 Flash

4096 x 16 SRAM

SSI

or

GPIO

6

INTERRUPT

CONTROLS

IPBB

CONTROLS

16

SCI0 & SCI1

External

Address Bus

Switch

16

A[00:15]

or

GPIO

COP

or

RESET

SPI0

COP/

Watchdog

4

16

External

Data Bus

Switch

SPI1

or

GPIO

External

Bus

Interface

Unit

MODULE CONTROLS

D[00:15]

Applica-

tion-Specific

Memory &

Peripherals

IPBus Bridge

(IPBB)

4

ADDRESS BUS [8:0]

DATA BUS [15:0]

PS Select[0]

DS Select[1]

WR Enable

RD Enable

Bus

Control

Dedicated

GPIO

16

56F826 Block Diagram

56F826 Technical Data, Rev. 14

Freescale Semiconductor

3

Part 1 Overview

1.1 56F826 Features

1.1.1

Processing Core

•

Efficient 16-bit 56800 family controller engine with dual Harvard architecture

As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency

Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

Two 36-bit accumulators, including extension bits

16-bit bidirectional barrel shifter

Parallel instruction set with unique processor addressing modes

Hardware DO and REP loops

Three internal address buses and one external address bus

Four internal data buses and one external data bus

Instruction set supports both DSP and controller functions

Controller-style addressing modes and instructions for compact code

Efficient C Compiler and local variable support

Software subroutine and interrupt stack with depth limited only by memory

JTAG/OnCE Debug Programming Interface

1.1.2

Memory

•

Harvard architecture permits as many as three simultaneous accesses to Program and Data memory

On-chip memory including a low-cost, high-volume Flash solution

— 31.5K × 16-bit words of Program Flash

•

— 512 × 16-bit words of Program RAM

— 2K × 16-bit words of Data Flash

— 4K × 16-bit words of Data RAM

— 2K × 16-bit words of BootFLASH

•

Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states

— As much as 64K × 16-bit Data memory

— As much as 64K × 16-bit Program memory

1.1.3

Peripheral Circuits for 56F826

•

One General Purpose Quad Timer totalling 7 pins

One Serial Peripheral Interface with 4 pins (or four additional GPIO lines)

One Serial Peripheral Interface, or multiplexed with two Serial Communications Interfaces

totalling 4 pins

•

Synchronous Serial Interface (SSI) with configurable six-pin port (or six additional GPIO lines)

56F826 Technical Data, Rev. 14

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Freescale Semiconductor

56F826 Description

•

Sixteen (16) dedicated General Purpose I/O (GPIO) pins

Thirty (30) shared General Purpose I/O (GPIO) pins

Computer-Operating Properly (COP) Watchdog timer

Two external interrupt pins

External reset pin for hardware reset

JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging

Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock

Fabricated in high-density EMOS with 5V-tolerant, TTL-compatible digital inputs

One Time of Day module

1.1.4

Energy Information

Dual power supply, 3.3V and 2.5V

Wait and Multiple Stop modes available

•

1.2 56F826 Description

The 56F826 is a member of the 56800 core-based family of processors. It combines, on a single chip, the

processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to

create an extremely cost-effective solution for general purpose applications. Because of its low cost,

configuration flexibility, and compact program code, the 56F826 is well-suited for many applications.

The 56F826 includes many peripherals that are especially useful for applications such as: noise

suppression, ID tag readers, sonic/subsonic detectors, security access devices, remote metering, sonic

alarms, POS terminals, feature phones.

The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in

parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming

model and optimized instruction set allow straightforward generation of efficient, compact code for both

DSP and MCU applications. The instruction set is also highly efficient for C/C++ Compilers to enable

rapid development of optimized control applications.

The 56F826 supports program execution from either internal or external memories. Two data operands can

be accessed from the on-chip Data RAM per instruction cycle. The 56F826 also provides two external

dedicated interrupt lines, and up to 46 General Purpose Input/Output (GPIO) lines, depending on

peripheral configuration.

The 56F826 controller includes 31.5K words (16-bit) of Program Flash and 2K words of Data Flash (each

programmable through the JTAG port) with 512 words of Program RAM, and 4K words of Data RAM. It

also supports program execution from external memory.

The 56F826 incorporates a total of 2K words of Boot Flash for easy customer-inclusion of

field-programmable software routines that can be used to program the main Program and Data Flash

memory areas. Both Program and Data Flash memories can be independently bulk-erased or erased in page

sizes of 256 words. The Boot Flash memory can also be either bulk- or page-erased.

56F826 Technical Data, Rev. 14

Freescale Semiconductor

5

This controller also provides a full set of standard programmable peripherals including one Synchronous

Serial Interface (SSI), one Serial Peripheral Interface (SPI), the option to select a second SPI or two Serial

Communications Interfaces (SCIs), and one Quad Timer. The SSI, SPI, and Quad Timer can be used as

General Purpose Input/Outputs (GPIOs) if a timer function is not required.

1.3 Award-Winning Development Environment

•

Processor Expert^TM(PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use

component-based software application creation with an expert knowledge system.

•

The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation,

compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards

will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable

tools solution for easy, fast, and efficient development.

1.4 Product Documentation

The four documents listed in Table 1-1 are required for a complete description and proper design with the

56F826. Documentation is available from local Freescale distributors, Freescale Semiconductor sales

offices, Freescale Literature Distribution Centers, or online at www.freescale.com.

Table 1-1 56F826 Chip Documentation

Topic

Description

Order Number

56800EFM

56800E

Detailed description of the 56800 family architecture,

and 16-bit core processor and the instruction set

Family Manual

DSP56F826/F827

User’s Manual

Detailed description of memory, peripherals, and

interfaces of the 56F826 and 56F827

DSP56F826-827UM

DSP56F826

56F826

Technical Data Sheet

Electrical and timing specifications, pin descriptions,

and package descriptions (this document)

56F826

Product Brief

Summary description and block diagram of the 56F826

core, memory, peripherals and interfaces

DSP56F826PB

DSP56F826E

56F826

Errata

Details any chip issues that might be present

56F826 Technical Data, Rev. 14

6

Freescale Semiconductor

Data Sheet Conventions

1.5 Data Sheet Conventions

This data sheet uses the following conventions:

OVERBAR

This is used to indicate a signal that is active when pulled low. For example, the RESET pin is

active when low.

“asserted”

“deasserted”

Examples:

A high true (active high) signal is high or a low true (active low) signal is low.

A high true (active high) signal is low or a low true (active low) signal is high.

Voltage¹

Signal/Symbol

Logic State

True

Signal State

Asserted

V_IL/V_OL

False

Deasserted

Asserted

V_IH/V_OH

V_IL/V_OL

True

False

Deasserted

1. Values for V_IL, V_OL, V_IH, and V_OHare defined by individual product specifications.

56F826 Technical Data, Rev. 14

Freescale Semiconductor

7

Part 2 Signal/Connection Descriptions

2.1 Introduction

The input and output signals of the 56F826 are organized into functional groups, as shown in Table 2-1

and as illustrated in Figure 2-1. Table 2-1 describes the signal or signals present on a pin.

Table 2-1 Functional Group Pin Allocations

Functional Group

Power (V_DD, V_{DDIO or}V_DDA

Ground (V_SS, V_{SSIO or}V_SSA

Number of Pins

(3,4,1)

)

(3,4,1)

PLL and Clock

Address Bus¹

3

16

Data Bus¹

16

Bus Control

4

Quad Timer Module Ports¹

JTAG/On-Chip Emulation (OnCE)

6

16

6

Dedicated General Purpose Input/Output

Synchronous Serial Interface (SSI) Port¹

Serial Peripheral Interface (SPI) Port¹

4

Serial Communications Interface (SCI) Ports

4

5

Interrupt and Program Control

1. Alternately, GPIO pins

56F826 Technical Data, Rev. 14

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Freescale Semiconductor

Introduction

V_DD

V_DDA

V_DDIO

V_SS

2.5V Power

3.3V Analog Power

3.3V Power

GPIOB0–7

GPIOD0–7

3

8

Dedicated

GPIO

1

4

Ground

4*

1

SRD (GPIOC0)

SRFS (GPIOC1)

SRCK (GPIOC2)

STD (GPIOC3)

STFS (GPIOC4)

STCK (GPIOC5)

V_SSA

V_SSIO

1

Analog Ground

Ground

4

SSI Port

or GPIO

56F826

EXTAL

XTAL (CLOCKIN)

CLKO

PLL

and

Clock

1

SCLK (GPIOF4)

MOSI (GPIOF5)

MISO (GPIOF6)

SS (GPIOF7)

1

SPI1 Port

or GPIO

A0-A7 (GPIOE)

A8-A15 (GPIOA)

8

External

Address Bus or

GPIO

External Data

Bus

D0–D15

TXD0 (SCLK0)

RXD0 (MOSI0)

TXD1 (MISO0)

RXD1 (SS0)

1

16

SCI0,SCI1

Port or

SPI0 Port

PS

DS

1

External

Bus Control

RD

WR

TA0 (GPIOF0)

TA1 (GPIOF1)

TA2 (GPIOF2)

TA3 (GPIOF3)

1

Quad Timer A

or GPIO

TCK

TMS

TDI

1

JTAG/OnCE™

Port

IRQA

TDO

TRST

DE

1

IRQB

Interrupt/

Program

Control

RESET

EXTBOOT

*Includes TCS pin, which is reserved for factory use and is tied to VSS

1

Figure 2-1 56F826 Signals Identified by Functional Group

1. Alternate pin functionality is shown in parentheses.

56F826 Technical Data, Rev. 14

Freescale Semiconductor

9

2.2 Signals and Package Information

All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always

enabled. Exceptions:

1. When a pin is owned by GPIO, then the pull-up may be disabled under software control.

2. TCK has a weak pull-down circuit always active.

Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP

Signal

Name

Pin No.

Type

Description

V_DD

20

64

94

59

V_DD

Power—These pins provide power to the internal structures of the chip, and are

generally connected to a 2.5V supply.

V_DD

V_DDA

Analog Power—This pin is a dedicated power pin for the analog portion of the

chip and should be connected to a low-noise 3.3V supply.

V_DDIO

V_SS

5

V_DDIO

V_SS

Power In/Out—These pins provide power to the I/O structures of the chip, and

are generally connected to a 3.3V supply.

30

57

80

19

63

95

60

6

GND—These pins provide grounding for the internal structures of the chip. All

should be attached to V_SS.

V_SS

V_SSA

V_SSIO

TCS

V_SSA

V_SSIO

Analog Ground—This pin supplies an analog ground.

GND In/Out—These pins provide grounding for the I/O ring on the chip. All

should be attached to V_SS.

31

58

81

99

Input/Output

(Schmitt)

TCS—This pin is reserved for factory use. It must be tied to V_SSfor normal use.

In block diagrams, this pin is considered an additional V_SS.

EXTAL

61

Input

External Crystal Oscillator Input—This input should be connected to a 4MHz

external crystal or ceramic resonator. For more information, please refer to

Section 3.6.

56F826 Technical Data, Rev. 14

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Freescale Semiconductor

Signals and Package Information

Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)

Signal

Name

Pin No.

Type

Description

XTAL

62

Output

Crystal Oscillator Output—This output connects the internal crystal oscillator

output to an external crystal or ceramic resonator. If an external clock source

over 4MHz is used, XTAL must be used as the input and EXTAL connected to

V_SS. For more information, please refer to Section 3.6.3.

External Clock Input—This input should be asserted when using an external

clock or ceramic resonator.

(CLOCKIN)

CLKO

Input

65

Output

Clock Output—This pin outputs a buffered clock signal. By programming the

CLKO Select Register (CLKOSR), the user can select between outputting a

version of the signal applied to XTAL and a version of the device master clock at

the output of the PLL. The clock frequency on this pin can be disabled by

programming the CLKO Select Register (CLKOSR).

A0

(GPIOE0)

24

23

22

21

18

17

16

15

Output

Address Bus—A0–A7 specify the address for external program or data memory

accesses.

A1

(GPIOE1)

Input/Output

Port E GPIO—These eight General Purpose I/O (GPIO) pins can be individually

programmed as input or output pins.

A2

(GPIOE2)

After reset, the default state is Address Bus.

A3

(GPIOE3)

A4

(GPIOE4)

A5

(GPIOE5)

A6

(GPIOE6)

A7

(GPIOE7)

56F826 Technical Data, Rev. 14

Freescale Semiconductor

11

Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)

Signal

Name

Pin No.

Type

Description

A8

14

Output

Address Bus—A8–A15 specify the address for external program or data

(GPIOA0)

memory accesses.

A9

(GPIOA1)

13

12

11

10

9

Input/Output

Port A GPIO—These eight General Purpose I/O (GPIO) pins can be individually

programmed as input or output pins.

A10

(GPIOA2)

After reset, the default state is Address Bus.

A11

(GPIOA3)

A12

(GPIOA4)

A13

(GPIOA5)

A14

8

(GPIOA6)

A15

7

(GPIOA7)

D0

D1

34

35

36

37

38

39

40

41

42

43

44

46

47

48

49

50

29

Input/Output

Data Bus— D0–D15 specify the data for external program or data memory

accesses. D0–D15 are tri-stated when the external bus is inactive.

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

PS

Output

Program Memory Select—PS is asserted low for external program memory

access.

DS

28

Data Memory Select—DS is asserted low for external data memory access.

56F826 Technical Data, Rev. 14

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Freescale Semiconductor

Signals and Package Information

Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)

Signal

Name

Pin No.

Type

Description

RD

26

Output

Read Enable—RD is asserted during external memory read cycles. When RD is

asserted low, pins D0–D15 become inputs and an external device is enabled

onto the device data bus. When RD is deasserted high, the external data is

latched inside the device. When RD is asserted, it qualifies the A0–A15, PS, and

DS pins. RD can be connected directly to the OE pin of a Static RAM or ROM.

WR

27

Output

Write Enable—WR is asserted during external memory write cycles. When WR

is asserted low, pins D0–D15 become outputs and the device puts data on the

bus. When WR is deasserted high, the external data is latched inside the

external device. When WR is asserted, it qualifies the A0–A15, PS, and DS pins.

WR can be connected directly to the WE pin of a Static RAM.

TA0

(GPIOF0)

91

90

Input/Output

TA0–3—Timer A Channels 0, 1, 2, and 3

Port F GPIO—These four General Purpose I/O (GPIO) pins can be individually

programmed as input or output.

TA1

(GPIOF1)

After reset, the default state is Quad Timer.

TA2

89

(GPIOF2)

TA3

88

(GPIOF3)

TCK

100

Input

(Schmitt)

Test Clock Input—This input pin provides a gated clock to synchronize the test

logic and shift serial data to the JTAG/OnCE port. The pin is connected internally

to a pull-down resistor.

TMS

1

Input

(Schmitt)

Test Mode Select Input—This input pin is used to sequence the JTAG TAP

controller’s state machine. It is sampled on the rising edge of TCK and has an

on-chip pull-up resistor.

Note: Always tie the TMS pin to V_DDthrough a 2.2K resistor.

TDI

TDO

TRST

2

3

4

Input

(Schmitt)

Test Data Input—This input pin provides a serial input data stream to the

JTAG/OnCE port. It is sampled on the rising edge of TCK and has an on-chip

pull-up resistor.

Output

Test Data Output—This tri-statable output pin provides a serial output data

stream from the JTAG/OnCE port. It is driven in the Shift-IR and Shift-DR

controller states, and changes on the falling edge of TCK.

Input

(Schmitt)

Test Reset—As an input, a low signal on this pin provides a reset signal to the

JTAG TAP controller. To ensure complete hardware reset, TRST should be

asserted whenever RESET is asserted. The only exception occurs in a

debugging environment when a hardware device reset is required and it is

necessary not to reset the JTAG/OnCE module. In this case, assert RESET, but

do not assert TRST. TRST must always be asserted at power-up.

Note: For normal operation, connect TRST directly to V_SS. If the design is to be used

in a debugging environment, TRST may be tied to V_SSthrough a 1K resistor.

DE

98

Output

Debug Event—DE provides a low pulse on recognized debug events.

56F826 Technical Data, Rev. 14

Freescale Semiconductor

13

Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)

Signal

Name

Pin No.

Type

Description

GPIOB0

GPIOB1

GPIOB2

GPIOB3

GPIOB4

GPIOB5

GPIOB6

GPIOB7

GPIOD0

GPIOD1

GPIOD2

GPIOD3

GPIOD4

GPIOD5

GPIOD6

GPIOD7

SRD

66

67

68

69

70

71

72

73

74

75

76

77

78

79

82

83

51

Input or

Output

Port B GPIO—These eight dedicated General Purpose I/O (GPIO) pins can be

individually programmed as input or output pins.

After reset, the default state is GPIO input.

Input or

Output

Port D GPIO—These eight dedicated GPIO pins can be individually

programmed as an input or output pins.

After reset, the default state is GPIO input.

Input/Output

SSI Receive Data (SRD)—This input pin receives serial data and transfers the

data to the SSI Receive Shift Receiver.

(GPIOC0)

SRFS

Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of

being individually programmed as input or output.

After reset, the default state is GPIO input.

52

Input/ Output SSI Serial Receive Frame Sync (SRFS)—This bidirectional pin is used by the

receive section of the SSI as frame sync I/O or flag I/O. The STFS can be used

only by the receiver. It is used to synchronize data transfer and can be an input

or an output.

(GPIOC1)

Input/Output

Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of

being individually programmed as input or output.

After reset, the default state is GPIO input.

56F826 Technical Data, Rev. 14

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Freescale Semiconductor

Signals and Package Information

Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)

Signal

Name

Pin No.

Type

Description

SRCK

53

Input/Output

SSI Serial Receive Clock (SRCK)—This bidirectional pin provides the serial bit

rate clock for the Receive section of the SSI. The clock signal can be continuous

or gated and can be used by both the transmitter and receiver in synchronous

mode.

(GPIOC2)

Input/Output

Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of

being individually programmed as input or output.

After reset, the default state is GPIO input.

STD

54

55

Output

SSI Transmit Data (STD)—This output pin transmits serial data from the SSI

Transmitter Shift Register.

(GPIOC3)

Input/Output

Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of

being individually programmed as input or output.

After reset, the default state is GPIO input.

STFS

Input

SSI Serial Transmit Frame Sync (STFS)—This bidirectional pin is used by the

Transmit section of the SSI as frame sync I/O or flag I/O. The STFS can be used

by both the transmitter and receiver in synchronous mode. It is used to

synchronize data transfer and can be an input or output pin.

(GPIOC4)

STCK

Input/Output

Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of

being individually programmed as input or output.

After reset, the default state is GPIO input.

56

Input/ Output SSI Serial Transmit Clock (STCK)—This bidirectional pin provides the serial bit

rate clock for the transmit section of the SSI. The clock signal can be continuous

or gated. It can be used by both the transmitter and receiver in synchronous

mode.

(GPIOC5)

Input/Output

Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of

being individually programmed as input or output.

After reset, the default state is GPIO input.

SCLK

84

85

Input/Output

SPI Serial Clock—In master mode, this pin serves as an output, clocking slaved

listeners. In slave mode, this pin serves as the data clock input.

(GPIOF4)

Port F GPIO—This General Purpose I/O (GPIO) pin can be individually

programmed as input or output.

After reset, the default state is SCLK.

MOSI

Input/Output

SPI Master Out/Slave In (MOSI)—This serial data pin is an output from a

master device and an input to a slave device. The master device places data on

the MOSI line a half-cycle before the clock edge that the slave device uses to

latch the data.

(GPIOF5)

Port F GPIO—This General Purpose I/O (GPIO) pin can be individually

programmed as input or output.

56F826 Technical Data, Rev. 14

Freescale Semiconductor

15

Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)

Signal

Name

Pin No.

Type

Description

MISO

86

Input/Output

SPI Master In/Slave Out (MISO)—This serial data pin is an input to a master

device and an output from a slave device. The MISO line of a slave device is

placed in the high-impedance state if the slave device is not selected.

(GPIOF6)

Input/Output

Port F GPIO—This General Purpose I/O (GPIO) pin can be individually

programmed as input or output.

After reset, the default state is MISO.

SS

87

Input

SPI Slave Select—In master mode, this pin is used to arbitrate multiple masters.

In slave mode, this pin is used to select the slave.

(GPIOF7)

Input/Output

Port F GPIO—This General Purpose I/O (GPIO) pin can be individually

programmed as input or output.

After reset, the default state is SS.

TXD0

97

96

Output

Transmit Data (TXD0)—transmit data output

(SCLK0)

Input/Output

SPI Serial Clock—In master mode, this pin serves as an output, clocking slaved

listeners. In slave mode, this pin serves as the data clock input.

After reset, the default state is SCI output.

RXD0

Input

Receive Data (RXD0)— receive data input

(MOSI0)

Input/Output

SPI Master Out/Slave In—This serial data pin is an output from a master

device, and an input to a slave device. The master device places data on the

MOSI line one half-cycle before the clock edge the slave device uses to latch the

data.

After reset, the default state is SCI input.

TXD1

93

92

Output

Transmit Data (TXD1)—transmit data output

(MISO0)

Input/Output

SPI Master In/Slave Out—This serial data pin is an input to a master device and

an output from a slave device. The MISO line of a slave device is placed in the

high-impedance state if the slave device is not selected.

After reset, the default state is SCI output.

RXD1

(SS0)

Input

(Schmitt)

Receive Data (RXD1)— receive data input

Input

SPI Slave Select—In master mode, this pin is used to arbitrate multiple masters.

In slave mode, this pin is used to select the slave.

After reset, the default state is SCI input.

56F826 Technical Data, Rev. 14

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Freescale Semiconductor

Signals and Package Information

Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)

Signal

Name

Pin No.

Type

Description

IRQA

32

Input

(Schmitt)

External Interrupt Request A—The IRQA input is a synchronized external

interrupt request that indicates that an external device is requesting service. It

can be programmed to be level-sensitive or negative-edge-triggered. If

level-sensitive triggering is selected, an external pull-up resistor is required for

wired-OR operation.

If the processor is in the Stop state and IRQA is asserted, the processor will exit

the Stop state.

IRQB

33

45

Input

(Schmitt)

External Interrupt Request B—The IRQB input is an external interrupt request

that indicates that an external device is requesting service. It can be

programmed to be level-sensitive or negative-edge-triggered. If level-sensitive

triggering is selected, an external pull-up resistor is required for wired-OR

operation.

RESET

Input

(Schmitt)

Reset—This input is a direct hardware reset on the processor. When RESET is

asserted low, the device is initialized and placed in the Reset state. A Schmitt

trigger input is used for noise immunity. When the RESET pin is deasserted, the

initial chip operating mode is latched from the external boot pin. The internal

reset signal will be deasserted synchronous with the internal clocks, after a fixed

number of internal clocks.

To ensure complete hardware reset, RESET and TRST should be asserted

together. The only exception occurs in a debugging environment when a

hardware device reset is required and it is necessary not to reset the

OnCE/JTAG module. In this case, assert RESET, but do not assert TRST.

EXTBOOT

25

Input

External Boot—This input is tied to V_DDto force device to boot from off-chip

(Schmitt)

memory. Otherwise, it is tied to ground.

56F826 Technical Data, Rev. 14

Freescale Semiconductor

17

Part 3 Specifications

3.1 General Characteristics

The 56F826 is fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term

“5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to

withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices

designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V- and 5V-compatible

I/O voltage levels. A standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during

normal operation without causing damage. This 5V-tolerant capability, therefore, offers the power savings

of 3.3V I/O levels while being able to receive 5V levels without being damaged.

Absolute maximum ratings given in Table 3-1 are stress ratings only, and functional operation at the

maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent

damage to the device.

The 56F826 DC/AC electrical specifications are preliminary and are from design simulations. These

specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized

specifications will be published after complete characterization and device qualifications have been

completed.

CAUTION

This device contains protective circuitry to guard against

damage due to high static voltage or electrical fields.

However, normal precautions are advised to avoid

application of any voltages higher than maximum rated

voltages to this high-impedance circuit. Reliability of

operation is enhanced if unused inputs are tied to an

appropriate voltage level.

56F826 Technical Data, Rev. 14

18

Freescale Semiconductor

General Characteristics

Table 3-1 Absolute Maximum Ratings

Characteristic

Symbol

Min

Max

V_SS+ 3.0

Unit

1

Supply voltage, core

V

V_DD

V_SS– 0.3

2

Supply voltage, IO

V_DDIO

V_SSIO– 0.3

V_SSA– 0.3

V

_SSIO+ 4.0

V

2

Supply voltage, Analog

V_DDA

V_SSA+ 4.0

V_IN

V_SSIO– 0.3

V_SSA– 0.3

V_SSIO+ 5.5

Digital input voltages

V_INA

V_DDA+ 0.3

Analog input voltages - XTAL, EXTAL

Voltage difference V_DDto V_{DD_IO}, V_DDA

ΔV_DD

ΔV_SS

I

- 0.3

—

0.3

10

V

Voltage difference V_SSto V_{SS _IO}, V_SSA

Current drain per pin excluding V_DD, V_SS,V_DDA, V_SSA,

V_DDIO, V_SSIO

mA

Junction temperature

T_J

—

150

°C

Storage temperature range

T_STG

–55

1. V_DDmust not exceed V_DDIO

2. V_DDIOand V_DDAmust not differ by more that 0.5V

Table 3-2 Recommended Operating Conditions

Characteristic

Supply voltage, core

Symbol

V_DD

Min

2.25

3.0

Typ

2.5

3.3

-

Max

2.75

3.6

0.1

85

Unit

V

Supply Voltage, IO and analog

V

_DDIO,V_DDA

Voltage difference V_DDto V_{DD_IO}, V_DDA

Voltage difference V_SSto V_{SS _IO}, V_SSA

ΔV_DD

-0.1

–40

V

ΔV_SS

-

V

Ambient operating temperature

T_A

–

°C

56F826 Technical Data, Rev. 14

Freescale Semiconductor

19

6

Table 3-3 Thermal Characteristics

Value

Characteristic

Symbol

Unit

Notes

Comments

100-pin LQFP

Junction to ambient

Natural convection

R_θJA

48.3

°C/W

2

Junction to ambient (@1m/sec)

R_θJMA

43.9

40.7

°C/W

2

Junction to ambient

Natural convection

Four layer board (2s2p)

R_θJMA

(2s2p)

1.2

Junction to ambient (@1m/sec) Four layer board (2s2p)

Junction to case

R_θJMA

R_θJC

Ψ_JT

38.6

13.5

°C/W

W

1,2

3

Junction to center of case

I/O pin power dissipation

1.0

4, 5

P _I/O

User Determined

P _D= (I_DDx V_DD+ P _I/O

(TJ - TA) /RθJA

Power dissipation

P _D

)

W

Junction to center of case

P_DMAX

W

7

Notes:

1. Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application.

Determined on 2s2p thermal test board.

2. Junction to ambient thermal resistance, Theta-JA (R ) was simulated to be equivalent to the JEDEC

θJA

specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was also simulated on

a thermal test board with two internal planes (2s2p, where “s” is the number of signal layers and “p” is the

number of planes) per JESD51-6 and JESD51-7. The correct name for Theta-JA for forced convection or with

the non-single layer boards is Theta-JMA.

3. Junction to case thermal resistance, Theta-JC (R ), was simulated to be equivalent to the measured values

θJC

using the cold plate technique with the cold plate temperature used as the “case” temperature. The basic cold

plate measurement technique is described by MIL-STD 883D, Method 1012.1. This is the correct thermal

metric to use to calculate thermal performance when the package is being used with a heat sink.

4. Thermal Characterization Parameter, Psi-JT (Ψ ), is the “resistance” from junction to reference point

JT

thermocouple on top center of case as defined in JESD51-2. Ψ is a useful value to use to estimate junction

JT

temperature in steady state customer environments.

5. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site

(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and

board thermal resistance.

6. See Section 5.1 for more details on thermal design considerations.

7. TJ = Junction Temperature

TA = Ambient Temperature

56F826 Technical Data, Rev. 14

20

Freescale Semiconductor

DC Electrical Characteristics

3.2 DC Electrical Characteristics

Table 3-4 DC Electrical Characteristics

Operating Conditions: V_SSIO=V_SS= V_SSA= 0V, V_DDA=V_DDIO=3.0–3.6V, V_DD= 2.25–2.75V, T_A= –40° to +85°C, C_L≤ 50pF, f_op= 80MHz

Characteristic

Input high voltage (XTAL/EXTAL)

Symbol

V_IHC

V_ILC

V_IHS

V_ILS

V_IH

Min

2.25

0

Typ

—

Max

3.6

0.5

5.5

0.8

5.5

0.8

1

Unit

V

Input low voltage (XTAL/EXTAL)

V

Input high voltage (Schmitt trigger inputs)¹

2.2

-0.3

2.0

-0.3

-1

V

Input low voltage (Schmitt trigger inputs)¹

Input high voltage (all other digital inputs)

V

Input low voltage (all other digital inputs)

V_IL

V

Input current high (pull-up/pull-down resistors disabled,

I_IH

μA

V_IN=V_DD

)

Input current low (pull-up/pull-down resistors disabled,

V_IN=V_SS

I_IL

-1

—

1

μA

)

Input current high (with pull-up resistor, V_IN=V_DD

Input current low (with pull-up resistor, V_IN=V_SS

Input current high (with pull-down resistor, V_IN=V_DD

)

I_IHPU

I_ILPU

I_IHPD

I_ILPD

-1

-210

20

—

30

—

1

-50

180

1

μA

KΩ

μA

)

Input current low (with pull-down resistor, V_IN=V_SS

Nominal pull-up or pull-down resistor value

Output tri-state current low

)

-1

R

_PU, R_PD

I_OZL

-10

-15

10

15

Output tri-state current high

2

I_OZH

I_IHA

Input current high (analog inputs, V_IN=V_DDA

)

2

I_ILA

-15

—

15

μA

Input current low (analog inputs, V_IN=V_SSA

Output High Voltage (at IOH)

Output Low Voltage (at IOL)

Output source current

)

V_OH

V_OL

I_OH

V_DD– 0.7

—

0.4

—

V

—

4

V

mA

Output sink current

I_OL

4

PWM pin output source current³

PWM pin output sink current⁴

I_OHP

I_OLP

10

16

56F826 Technical Data, Rev. 14

Freescale Semiconductor

21

Table 3-4 DC Electrical Characteristics (Continued)

Operating Conditions: V_SSIO=V_SS= V_SSA= 0V, V_DDA=V_DDIO=3.0–3.6V, V_DD= 2.25–2.75V, T_A= –40° to +85°C, C_L≤ 50pF, f_op= 80MHz

Characteristic

Symbol

C_IN

Min

—

Typ

8

Max

—

Unit

pF

Input capacitance

Output capacitance

C_OUT

—

12

—

pF

5

V_DDsupply current

I_DDT

Run ⁶

—

47

21

75

36

mA

Wait⁷

Stop

—

2

8

mA

V

Low Voltage Interrupt, V_DDIOpower supply⁸

Low Voltage Interrupt, V_DDpower supply⁹

Power on Reset¹⁰

V_EIO

V_EIC

2.4

2.7

3.0

2.0

—

2.2

1.7

2.4

2.0

V

V_POR

1.

1. Schmitt Trigger inputs are: EXTBOOT, IRQA, IRQB, RESET, TCS, TCK, TRST, TMS, TDI and RXD1

2. Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.

3. PWM pin output source current measured with 50% duty cycle.

4. PWM pin output sink current measured with 50% duty cycle.

5. I_DDT= I_DD+ I_DDA(Total supply current for V_DD+ V_DDA

)

6. Run (operating) I_DDmeasured using 4MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports configured as

inputs; measured with all modules enabled.

7. Wait I_DDmeasured using external square wave clock source (f_osc= 4MHz) into XTAL; all inputs 0.2V from rail; no DC loads;

less than 50pF on all outputs. C_L= 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly affects wait I_DD

measured with PLL enabled.

;

8. This low-voltage interrupt monitors the V_DDIOpower supply. If V_DDIOdrops below V_EIO, an interrupt is generated. Functionality

of the device is guaranteed under transient conditions when V_DDIO>V_EIO(between the minimum specified V_DDIOand the point when

the V_EIOinterrupt is generated).

9. This low-voltage interrupt monitors theV_DDpower supply. If V_DDIOdrops below V_EIC, an interrupt is generated. Functionality of

the device is guaranteed under transient conditions when V_DD>V_EIC(between the minimum specified V_DDand the point when the

V

_EICinterrupt is generated).

10. Power–on reset occurs whenever the V_DDpower supply drops below V_POR. While power is ramping up, this signal remains

active for as long as V_DDis below V_PORno matter how long the ramp-up rate is.

56F826 Technical Data, Rev. 14

22

Freescale Semiconductor

Supply Voltage Sequencing and Separation Cautions

100

75

IDD Analog

IDD Total

IDD Digital

50

25

0

20

60

80

40

Freq. (MHz)

Figure 3-1 Maximum Run IDD vs. Frequency (see Note 6. in Table 3-4)

3.3 Supply Voltage Sequencing and Separation Cautions

Figure 3-2 shows two situations to avoid in sequencing the V and V

V

supplies.

DD

DDIO, DDA

3.3V

V_DDIO,V_DDA

2

Supplies Stable

2.5V

V_DD

1

0

Time

Notes: 1. V_DDrising before V_DDIO, V_DDA

2. V_DDIO, V_DDArising much faster than V_DD

Figure 3-2 Supply Voltage Sequencing and Separation Cautions

56F826 Technical Data, Rev. 14

Freescale Semiconductor

23

V

should not be allowed to rise early (1). This is usually avoided by running the regulator for the V

DD

supply (2.5V) from the voltage generated by the 3.3V V

supply, see Figure 3-3. This keeps V from

DDIO

DD

rising faster than V

.

DDIO

V

should not rise so late that a large voltage difference is allowed between the two supplies (2).

DD

Typically this situation is avoided by using external discrete diodes in series between supplies, as shown

in Figure 3-3. The series diodes forward bias when the difference between V and V reaches

DDIO

DD

approximately 1.4, causing V to rise as V

ramps up. When the V regulator begins proper

DD

DDIO

DD

operation, the difference between supplies will typically be 0.8V and conduction through the diode chain

reduces to essentially leakage current. During supply sequencing, the following general relationship

should be adhered to:

V

> V > (V

- 1.4V)

DDIO

DD

DDIO

In practice, V

is typically connected directly to V

with some filtering.

DDA

DDIO

V_DDIO,V_DDA

3.3V

Regulator

Supply

V_DD

2.5V

Regulator

Figure 3-3 Example Circuit to Control Supply Sequencing

3.4 AC Electrical Characteristics

Timing waveforms in Section 3.4 are tested using the V_ILand V_IHlevels specified in the DC Characteristics

table. The levels of V_IHand V_ILfor an input signal are shown in Figure 3-4.

Pulse Width

Low

V_IL

High

V_IH

90%

Input Signal

50%

Midpoint1

10%

Fall Time

Note: The midpoint is V_IL+ (V_IH– V_IL)/2.

Rise Time

Figure 3-4 Input Signal Measurement References

Figure 3-5 shows the definitions of the following signal states:

•

Active state, when a bus or signal is driven, and enters a low impedance state

Tri-stated, when a bus or signal is placed in a high impedance state

Data Valid state, when a signal level has reached V_OLor V_OH

•

Data Invalid state, when a signal level is in transition between V_OLand V_OH

56F826 Technical Data, Rev. 14

24

Freescale Semiconductor

Flash Memory Characteristics

Data2 Valid

Data2

Data1 Valid

Data1

Data3 Valid

Data3

Data

Tri-stated

Data Invalid State

Data Active

Figure 3-5 Signal States

3.5 Flash Memory Characteristics

Table 3-5 Flash Memory Truth Table

XE¹

YE²

SE³

OE⁴

PROG⁵

ERASE⁶

MAS1⁷

NVSTR⁸

Mode

Standby

Read

L

H

L

H

L

H

L

H

L

H

L

H

Word Program

Page Erase

Mass Erase

L

H

L

1. X address enable, all rows are disabled when XE = 0

2. Y address enable, YMUX is disabled when YE = 0

3. Sense amplifier enable

4. Output enable, tri-state Flash data out bus when OE = 0

5. Defines program cycle

6. Defines erase cycle

7. Defines mass erase cycle, erase whole block

8. Defines non-volatile store cycle

Table 3-6 IFREN Truth Table

Mode

IFREN = 1

IFREN = 0

Read

Read information block

Program information block

Erase information block

Erase both block

Read main memory block

Program main memory block

Erase main memory block

Word program

Page erase

Mass erase

56F826 Technical Data, Rev. 14

Freescale Semiconductor

25

Table 3-7 Flash Timing Parameters

Operating Conditions: V_SS= V_SSA= 0 V, V_DD= V_DDA= 3.0–3.6V, T_A= –40° to +85°C, C_L≤ 50pF

Characteristic

Program time

Symbol

Min

20

Typ

Max

Unit

us

Figure

–

Figure 3-6

Figure 3-7

Figure 3-8

Tprog*

Terase*

Tme*

Erase time

20

–

ms

Mass erase time

100

10,000

10

ms

Endurance¹

E_CYC

20,000

30

cycles

years

Data Retention¹

D_RET

The following parameters should only be used in the Manual Word Programming Mode

PROG/ERASE to NVSTR set

up time

–

5

–

us

Figure 3-6,

Figure 3-7,

Figure 3-8

Tnvs*

NVSTR hold time

Figure 3-6,

Figure 3-7

Tnvh*

NVSTR hold time (mass erase)

NVSTR to program set up time

Recovery time

–

100

10

1

–

us

Figure 3-8

Figure 3-6

Tnvh1*

Tpgs*

Trcv*

Figure 3-6,

Figure 3-7,

Figure 3-8

Cumulative program

HV period²

–

3

–

ms

Figure 3-6

Thv

Program hold time³

–

Figure 3-6

Tpgh

Tads

Tadh

Address/data set up time³

Address/data hold time³

1. One cycle is equal to an erase program and read.

2. Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot be

programmed twice before next erase.

3. Parameters are guaranteed by design in smart programming mode and must be one cycle or greater.

*The Flash interface unit provides registers for the control of these parameters.

56F826 Technical Data, Rev. 14

26

Freescale Semiconductor

Flash Memory Characteristics

IFREN

XADR

XE

Tadh

YADR

YE

DIN

Tads

PROG

NVSTR

Tnvs

Tprog

Tpgh

Tpgs

Tnvh

Trcv

Thv

Figure 3-6 Flash Program Cycle

IFREN

XADR

XE

YE=SE=OE=MAS1=0

ERASE

NVSTR

Tnvs

Tnvh

Trcv

Terase

Figure 3-7 Flash Erase Cycle

56F826 Technical Data, Rev. 14

Freescale Semiconductor

27

IFREN

XADR

XE

MAS1

YE=SE=OE=0

ERASE

NVSTR

Tnvs

Tnvh1

Trcv

Tme

Figure 3-8 Flash Mass Erase Cycle

3.6 External Clock Operation

The 56F826 system clock can be derived from a crystal or an external system clock signal. To generate a

reference frequency using the internal oscillator, a reference crystal must be connected between the

EXTAL and XTAL pins.

3.6.1

Crystal Oscillator

The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the

frequency range specified for the external crystal in Table 3-9. A recommended crystal oscillator circuit

is shown in Figure 3-9. Follow the crystal supplier’s recommendations when selecting a crystal, because

crystal parameters determine the component values required to provide maximum stability and reliable

start-up. The crystal and associated components should be mounted as close as possible to the EXTAL

and XTAL pins to minimize output distortion and start-up stabilization time.The internal 56F82x

oscillator circuitry is designed to have no external load capacitors present. As shown in Figure 3-9, no

external load capacitors should be used.

The 56F80x components internally are modeled as a parallel resonant oscillator circuit to provide a

capacitive load on each of the oscillator pins (XTAL and EXTAL) of 10pF to 13pF over temperature and

process variations. Using a typical value of internal capacitance on these pins of 12pF and a value of 3pF

56F826 Technical Data, Rev. 14

28

Freescale Semiconductor

External Clock Operation

as a typical circuit board trace capacitance the parallel load capacitance presented to the crystal is 9pF as

determined by the following equation:

CL1 * CL2

CL1 + CL2

12 * 12

12 + 12

CL =

+ Cs =

+ 3 = 6 + 3 = 9pF

This is the value load capacitance that should be used when selecting a crystal and determining the actual

frequency of operation of the crystal oscillator circuit.

Recommended External Crystal

Parameters:

R_z= 1 to 3MΩ

EXTAL XTAL

R_z

f_c= 4Mhz (optimized for 4MHz)

f_c

Figure 3-9 Connecting to a Crystal Oscillator Circuit

3.6.2

Ceramic Resonator

It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system

design can tolerate the reduced signal integrity. A typical ceramic resonator circuit is shown in

Figure 3-10. Refer to supplier’s recommendations when selecting a ceramic resonator and associated

components. The resonator and components should be mounted as close as possible to the EXTAL and

XTAL pins. The internal 56F82x oscillator circuitry is designed to have no external load capacitors

present. As shown in Figure 3-10, no external load capacitors should be used.

Recommended Ceramic Resonator

Parameters:

R_z= 1 to 3 MΩ

EXTAL XTAL

R_z

f_c= 4Mhz (optimized for 4MHz)

f_c

Figure 3-10 Connecting a Ceramic Resonator

Note: Freescale recommends only two terminal ceramic resonators vs. three terminal resonators

(which contain an internal bypass capacitor to ground).

56F826 Technical Data, Rev. 14

Freescale Semiconductor

29

3.6.3

External Clock Source

The recommended method of connecting an external clock is given in Figure 3-11. The external clock

source is connected to XTAL and the EXTAL pin is held V

/2.

DDA

56F826

XTAL

EXTAL

V

/2

External

Clock

DDA

Figure 3-11 Connecting an External Clock Signal

Table 3-8 External Clock Operation Timing Requirements

Operating Conditions: V_SSIO=V_SS= V_SSA= 0V, V_DDA=V_DDIO=3.0–3.6V, V_DD= 2.25–2.75V, T_A= –40° to +85°C, C_L≤ 50pF, f_op= 80MHz

Characteristic

Symbol

f_osc

Min

0

Typ

4

Max

Unit

MHz

ns

Frequency of operation (external clock driver)¹

Clock Pulse Width^{3, 4}

80²

—

t_PW

6.25

—

1. See Figure 3-11 for details on using the recommended connection of an external clock driver.

2. When using Time of Day (TOD), maximum external frequency is 6MHz.

3. The high or low pulse width must be no smaller than 6.25ns or the chip will not function.

4. Parameters listed are guaranteed by design.

V_IH

External

Clock

90%

50%

10%

90%

50%

10%

t_PW

V_IL

Note: The midpoint is V_IL+ (V_IH– V_IL)/2.

Figure 3-12 External Clock Timing

56F826 Technical Data, Rev. 14

30

Freescale Semiconductor

External Bus Asynchronous Timing

3.6.4

Phase Locked Loop Timing

Table 3-9 PLL Timing

Operating Conditions: V_SSIO= V_SS= V_SSA= 0V, V_DDA= V_DDIO= 3.0–3.6V, V_DD= 2.25–2.75V, T_A= –40° to +85°C, C_L< 50pF, f_op= 80MHz

Characteristic

Symbol

f_osc

Min

2

Typ

4

Max

6

Unit

MHz

ms

External reference crystal frequency for the PLL¹

PLL output frequency²

f_out/2

t_plls

40

—

1

110

10

PLL stabilization time ³-40^oto +85^oC

1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work

correctly. The PLL is optimized for 4MHz input crystal.

2. ZCLK may not exceed 80MHz. For additional information on ZCLK and f_out/2, please refer to the OCCS chapter in the

User Manual. ZCLK = f_op

3. This is the minimum time required after the PLL set-up is changed to ensure reliable operation.

3.7 External Bus Asynchronous Timing

1, 2

Table 3-10 External Bus Asynchronous Timing

Operating Conditions: V_SSIO= V_SS= V_SSA= 0V, V_DDA= V_DDIO= 3.0–3.6V, V_DD= 2.25–2.75V, T_A= –40° to +85°C, C_L≤ 50pF, f_op= 80MHz

Characteristic

Symbol

Unit

Min

Max

Address Valid to WR Asserted

t_AWR

t_WR

6.5

—

ns

WR Width Asserted

Wait states = 0

Wait states > 0

7.5

—

ns

(T*WS) + 7.5

WR Asserted to D0–D15 Out Valid

t_WRD

t_DOH

t_DOS

—

T + 4.2

—

ns

Data Out Hold Time from WR Deasserted

4.8

Data Out Set Up Time to WR Deasserted

Wait states = 0

Wait states > 0

2.2

—

ns

(T*WS) + 6.4

RD Deasserted to Address Not Valid

t_RDA

0

—

ns

Address Valid to RD Deasserted

Wait states = 0

Wait states > 0

t_ARDD

18.7

(T*WS) + 18.7

ns

56F826 Technical Data, Rev. 14

Freescale Semiconductor

31

1, 2

Table 3-10 External Bus Asynchronous Timing

(Continued)

Operating Conditions: V_SSIO= V_SS= V_SSA= 0V, V_DDA= V_DDIO= 3.0–3.6V, V_DD= 2.25–2.75V, T_A= –40° to +85°C, C_L≤ 50pF, f_op= 80MHz

Characteristic

Symbol

Unit

Min

Max

Input Data Hold to RD Deasserted

t_DRD

t_RD

0

—

ns

RD Assertion Width

Wait states = 0

Wait states > 0

19

—

ns

(T*WS) + 19

Address Valid to Input Data Valid

Wait states = 0

Wait states > 0

t_AD

—

1

ns

(T*WS) + 1

Address Valid to RD Asserted

t_ARDA

t_RDD

-4.4

—

ns

RD Asserted to Input Data Valid

Wait states = 0

Wait states > 0

—

2.4

ns

(T*WS) + 2.4

WR Deasserted to RD Asserted

RD Deasserted to RD Asserted

WR Deasserted to WR Asserted

RD Deasserted to WR Asserted

t_WRRD

t_RDRD

t_WRWR

t_RDWR

6.8

0

—

ns

14.1

12.8

1. Timing is both wait state- and frequency-dependent. In the formulas listed, WS = the number of wait states and

T = Clock Period. For 80MHz operation, T = 12.5ns.

2. Parameters listed are guaranteed by design.

To calculate the required access time for an external memory for any frequency < 80Mhz, use this formula:

Top = Clock period @ desired operating frequency

WS = Number of wait states

Memory Access Time = (Top*WS) + (Top- 11.5)

56F826 Technical Data, Rev. 14

32

Freescale Semiconductor

External Bus Asynchronous Timing

A0–A15,

PS, DS

t_ARDD

(See Note)

t_RDA

t_ARDA

t_RDRD

t_RD

t_AWR

t_WRWR

RD

t_WRRD

t_WR

t_RDWR

WR

t_RDD

t_AD

t_DOH

t_WRD

t_DRD

t_DOS

Data Out

Data In

D0–D15

Note: During read-modify-write instructions and internal instructions, the address lines do not change state.

Figure 3-13 External Bus Asynchronous Timing

56F826 Technical Data, Rev. 14

Freescale Semiconductor

33

3.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing

1, 5

Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Operating Conditions: V_SSIO= V_SS= V_SSA= 0V, V_DDA= V_DDIO= 3.0–3.6V, V_DD= 2.25–2.75V, T_A= –40° to +85°C, C_L≤ 50pF, f_op= 80MHz

Characteristic

Symbol

Min

Max

Unit

See Figure

Figure 3-14

RESET Assertion to Address, Data and Control

Signals High Impedance

t_RAZ

—

21

ns

Minimum RESET Assertion Duration²

OMR Bit 6 = 0

OMR Bit 6 = 1

t_RA

Figure 3-14

275,000T

128T

—

ns

RESET Deassertion to First External Address Output

Edge-sensitive Interrupt Request Width

t_RDA

t_IRW

t_IDM

33T

1.5T

15T

34T

—

ns

Figure 3-14

Figure 3-15

Figure 3-16

IRQA, IRQB Assertion to External Data Memory

Access Out Valid, caused by first instruction execution

in the interrupt service routine

—

IRQA, IRQB Assertion to General Purpose Output

Valid, caused by first instruction execution in the

interrupt service routine

t_IG

16T

—

ns

Figure 3-16

Figure 3-17

IRQA Low to First Valid Interrupt Vector Address Out

recovery from Wait State³

t_IRI

13T

2T

—

ns

IRQA Width Assertion to Recover from Stop State⁴

t_IW

t_IF

Figure 3-18

Delay from IRQA Assertion to Fetch of first instruction

(exiting Stop)

OMR Bit 6 = 0

OMR Bit 6 = 1

—

275,000T

12T

ns

Duration for Level Sensitive IRQA Assertion to Cause

the Fetch of First IRQA Interrupt Instruction (exiting

Stop)

OMR Bit 6 = 0

OMR Bit 6 = 1

t_IRQ

Figure 3-19

—

275,000T

12T

ns

Delay from Level Sensitive IRQA Assertion to First

Interrupt Vector Address Out Valid (exiting Stop)

OMR Bit 6 = 0

t_II

—

275,000T

12T

ns

OMR Bit 6 = 1

1. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.

2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:

• After power-on reset

• When recovering from Stop state

3. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not

the minimum required so that the IRQA interrupt is accepted.

4. The interrupt instruction fetch is visible on the pins only in Mode 3.

5. Parameters listed are guaranteed by design.

56F826 Technical Data, Rev. 14

34

Freescale Semiconductor

Reset, Stop, Wait, Mode Select, and Interrupt Timing

RESET

t_RA

t_RAZ

t_RDA

A0–A15,

D0–D15

First Fetch

PS, DS,

RD, WR

First Fetch

Figure 3-14 Asynchronous Reset Timing

IRQA,

IRQB

t_IRW

Figure 3-15 External Interrupt Timing (Negative-Edge-Sensitive)

A0–A15,

PS, DS,

RD, WR

First Interrupt Instruction Execution

t_IDM

IRQA,

IRQB

a) First Interrupt Instruction Execution

General

Purpose

I/O Pin

t_IG

IRQA,

IRQB

b) General Purpose I/O

Figure 3-16 External Level-Sensitive Interrupt Timing

56F826 Technical Data, Rev. 14

Freescale Semiconductor

35

IRQA,

IRQB

t_IRI

A0–A15,

PS, DS,

RD, WR

First Interrupt Vector

Instruction Fetch

Figure 3-17 Interrupt from Wait State Timing

t_IW

IRQA

t_IF

A0–A15,

PS, DS,

RD, WR

First Instruction Fetch

Not IRQA Interrupt Vector

Figure 3-18 Recovery from Stop State Using Asynchronous Interrupt Timing

t_IRQ

IRQA

t_II

A0–A15

PS, DS,

RD, WR

First IRQA Interrupt

Instruction Fetch

Figure 3-19 Recovery from Stop State Using IRQA Interrupt Service

56F826 Technical Data, Rev. 14

36

Freescale Semiconductor

Serial Peripheral Interface (SPI) Timing

3.9 Serial Peripheral Interface (SPI) Timing

1

Table 3-12 SPI Timing

Operating Conditions: V_SSIO=V_SS= V_SSA= 0V, V_DDA=V_DDIO=3.0–3.6V, V_DD= 2.25–2.75V, T_A= –40° to +85°C, C_L≤ 50pF, f_op= 80MHz

Characteristic

Symbol

Min

Max

Unit

See Figure

Cycle time

Master

Slave

t_C

Figures

3-20, 3-21,

3-22, 3-23

50

25

—

ns

Enable lead time

Master

Slave

t_ELD

t_ELG

t_CH

t_CL

Figure 3-23

—

25

—

ns

Enable lag time

Master

Slave

Figure 3-23

—

100

—

ns

Clock (SCLK) high time

Master

Slave

ns

Figures

3-20, 3-21,

3-22, 3-23

24

12

—

Clock (SCLK) low time

Master

Slave

Figures

3-20, 3-21,

3-22, 3-23

24.1

12

—

ns

Data set-up time required for inputs

Master

Slave

t_DS

Figures

3-20, 3-21,

3-22, 3-23

20

0

—

ns

Data hold time required for inputs

Master

Slave

t_DH

Figures

3-20, 3-21,

3-22, 3-23

0

2

—

ns

Access time (time to data active from high-impedance state)

Slave

t_A

t_D

Figure 3-23

4.8

3.7

15

ns

Disable time (hold time to high-impedance state)

Slave

Figure 3-23

15.2

Data Valid for outputs

Master

Slave (after enable edge)

t_DV

Figures

3-20, 3-21,

3-22, 3-23

—

4.5

20.4

ns

Data invalid

Master

Slave

t_DI

t_R

t_F

Figures

3-20, 3-21,

3-22, 3-23

0

—

ns

Rise time

Master

Slave

Figures

3-20, 3-21,

3-22, 3-23

—

11.5

10.0

ns

Fall time

Master

Slave

Figures

3-20, 3-21,

3-22, 3-23

—

9.7

9.0

ns

1. Parameters are guaranteed by design.

56F826 Technical Data, Rev. 14

Freescale Semiconductor

37

SS

(Input)

SS is held High on master

t_C

t_R

t_F

t_CL

SCLK (CPOL = 0)

(Output)

t_CH

t_CL

t_F

t_R

SCLK (CPOL = 1)

(Output)

t_DH

t_CH

t_DS

MISO

(Input)

MSB in

t_DI

Bits 14–1

LSB in

t_DI(ref)

t_DV

MOSI

(Output)

Master MSB out

t_F

Bits 14–1

Master LSB out

t_R

Figure 3-20 SPI Master Timing (CPHA = 0)

SS

(Input)

SS is held High on master

t_C

t_F

t_R

t_CL

SCLK (CPOL = 0)

(Output)

t_CH

t_CL

t_F

SCLK (CPOL = 1)

(Output)

t_CH

t_DS

t_DH

t_R

MISO

(Input)

MSB in

t_DI

Bits 14–1

LSB in

t_DV

t_DV(ref)

MOSI

(Output)

Master MSB out

t_F

Bits 14– 1

Master LSB out

t_R

Figure 3-21 SPI Master Timing (CPHA = 1)

56F826 Technical Data, Rev. 14

38

Freescale Semiconductor

Serial Peripheral Interface (SPI) Timing

SS

(Input)

t_C

t_F

t_R

t_ELG

t_CL

SCLK (CPOL = 0)

(Input)

t_CH

t_CL

t_ELD

SCLK (CPOL = 1)

(Input)

t_F

t_CH

t_A

t_R

t_D

MISO

(Output)

Slave MSB out

Bits 14–1

t_DV

Slave LSB out

t_DI

t_DS

t_DI

t_DH

MOSI

(Input)

MSB in

Bits 14–1

LSB in

Figure 3-22 SPI Slave Timing (CPHA = 0)

SS

(Input)

t_C

t_F

t_R

t_CL

SCLK (CPOL = 0)

(Input)

t_CH

t_ELG

t_ELD

t_CL

SCLK (CPOL = 1)

(Input)

t_DV

t_CH

t_R

t_D

t_F

t_A

MISO

(Output)

Slave MSB out

Bits 14–1

t_DV

Slave LSB out

t_DS

t_DI

t_DH

MOSI

(Input)

MSB in

Bits 14–1

LSB in

Figure 3-23 SPI Slave Timing (CPHA = 1)

56F826 Technical Data, Rev. 14

Freescale Semiconductor

39

3.10 Synchronous Serial Interface (SSI) Timing

1

Table 3-13 SSI Master Mode Switching Characteristics

Operating Conditions: V_SSIO= V_SS= V_SSA= 0V, V_DDA= V_DDIO= 3.0–3.6V, V_DD= 2.25–2.75V, T_A= –40° to +85°C, C_L≤ 50pF, f_op= 80MHz

Parameter

Symbol

Min

Typ

Max

Units

10²

—

STCK frequency

fs

MHz

STCK period³

t_SCKW

t_SCKH

t_SCKL

100

50⁴

—

ns

STCK high time

—

50⁴

—

STCK low time

4

Output clock rise/fall time (STCK, SRCK)

—

ns

Delay from STCK high to STFS (bl) high - Master⁵

Delay from STCK high to STFS (wl) high - Master⁵

Delay from SRCK high to SRFS (bl) high - Master⁵

Delay from SRCK high to SRFS (wl) high - Master⁵

Delay from STCK high to STFS (bl) low - Master⁵

Delay from STCK high to STFS (wl) low - Master⁵

Delay from SRCK high to SRFS (bl) low - Master⁵

t_TFSBHM

t_TFSWHM

t_RFSBHM

t_RFSWHM

t_TFSBLM

t_TFSWLM

t_RFSBLM

t_RFSWLM

t_TXEM

0.1

—

0.5

0.1

0.6

-1.0

-0.1

20

0.5

1.3

-0.1

0

ns

Delay from SRCK high to SRFS (wl) low - Master⁵

0

STCK high to STXD enable from high impedance - Master

22

STCK high to STXD valid - Master

t_TXVM

24

26

STCK high to STXD not valid - Master

STCK high to STXD high impedance - Master

SRXD Setup time before SRCK low - Master

SRXD Hold time after SRCK low - Master

t_TXNVM

t_TXHIM

0.1

24

0.2

25.5

—

t_SM

4

t_HM

4

—

Synchronous Operation (in addition to standard internal clock parameters)

SRXD Setup time before STCK low - Master

SRXD Hold time after STCK low - Master

t_TSM

t_THM

4

—

1. Master mode is internally generated clocks and frame syncs

2. Max clock frequency is IP_clk/4 = 40MHz / 4 = 10MHz for an 80MHz part.

56F826 Technical Data, Rev. 14

40

Freescale Semiconductor

Synchronous Serial Interface (SSI) Timing

3. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)

and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync have

been inverted, all the timings remain valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS in the

tables and in the figures.

4. 50% duty cycle

5. bl = bit length; wl = word length

t_SCKW

t_SCKH

t_SCKL

STCK output

t_TFSBHM

t_TFSBLM

STFS (bl) output

STFS (wl) output

t_TFSWHM

t_TFSWLM

t_TXVM

t_TXEM

t_TXNVM

t_TXHIM

First Bit

Last Bit

STXD

SRCK output

t_RFSBHM

t_RFBLM

SRFS (bl) output

SRFS (wl) output

t_RFSWHM

t_RFSWLM

t_TSM

t_SM

t_HM

t_THM

SRXD

Figure 3-24 Master Mode Timing Diagram

56F826 Technical Data, Rev. 14

Freescale Semiconductor

41

1

Table 3-14 SSI Slave Mode Switching Characteristics

Operating Conditions: V_SSIO= V_SS= V_SSA= 0V, V_DDA= V_DDIO= 3.0–3.6V, V_DD= 2.25–2.75V, T_A= –40° to +85°C, C_L≤ 50pF, f_op= 80MHz

Parameter

Symbol

fs

Min

Typ

—

Max

Units

MHz

ns

10²

—

STCK frequency

STCK period³

t_SCKW

t_SCKH

t_SCKL

100

50⁴

—

STCK high time

—

ns

50⁴

—

STCK low time

—

ns

Output clock rise/fall time

TBD

—

ns

Delay from STCK high to STFS (bl) high - Slave⁵

Delay from STCK high to STFS (wl) high - Slave⁵

Delay from SRCK high to SRFS (bl) high - Slave⁵

Delay from SRCK high to SRFS (wl) high - Slave⁵

Delay from STCK high to STFS (bl) low - Slave⁵

Delay from STCK high to STFS (wl) low - Slave⁵

Delay from SRCK high to SRFS (bl) low - Slave⁵

t_TFSBHS

t_TFSWHS

t_RFSBHS

t_RFSWHS

t_TFSBLS

t_TFSWLS

t_RFSBLS

t_RFSWLS

t_TXES

0.1

—

46

0.1

-1

—

46

—

25

ns

-1

-46

Delay from SRCK high to SRFS (wl) low - Slave⁵

STCK high to STXD enable from high impedance - Slave

STCK high to STXD valid - Slave

t_TXVS

1

STFS high to STXD enable from high impedance (first bit) -

Slave

t_FTXES

5.5

STFS high to STXD valid (first bit) - Slave

STCK high to STXD not valid - Slave

t_FTXVS

t_TXNVS

t_TXHIS

t_SS

6

11

4

—

27

13

ns

STCK high to STXD high impedance - Slave

SRXD Setup time before SRCK low - Slave

SRXD Hold time after SRCK low - Slave

28.5

—

t_HS

4

—

56F826 Technical Data, Rev. 14

42

Freescale Semiconductor

Synchronous Serial Interface (SSI) Timing

1

Table 3-14 SSI Slave Mode Switching Characteristics

Operating Conditions: V_SSIO= V_SS= V_SSA= 0V, V_DDA= V_DDIO= 3.0–3.6V, V_DD= 2.25–2.75V, T_A= –40° to +85°C, C_L≤ 50pF, f_op= 80MHz

Parameter

Symbol

Min

Typ

Max

Units

Synchronous Operation (in addition to standard external clock parameters)

SRXD Setup time before STCK low - Slave

SRXD Hold time after STCK low - Slave

t_TSS

t_THS

4

—

1. Slave mode is externally generated clocks and frame syncs

2. Max clock frequency is IP_clk/4 = 40MHz / 4 = 10MHz for an 80MHz part.

3. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)

and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync

have been inverted, all the timings remain valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS

in the tables and in the figures.

4. 50% duty cycle

5. bl = bit length; wl = word length

56F826 Technical Data, Rev. 14

Freescale Semiconductor

43

t_SCKW

t_SCKH

t_SCKL

STCK input

STFS (bl) input

STFS (wl) input

t_TFSBLS

t_TFSBHS

t_TFSWHS

t_TFSWLS

t_FTXVS

t_FTXES

t_TXVS

t_TXNVS

t_TXES

t_TXHIS

First Bit

Last Bit

STXD

SRCK input

t_RFBLS

t_RFSBHS

SRFS (bl) input

SRFS (wl) input

t_RFSWHS

t_RFSWLS

t_TSS

t_SS

t_HS

t_THS

SRXD

Figure 3-25 Slave Mode Clock Timing

3.11 Quad Timer Timing

1, 2

Table 3-15 Timer Timing

Operating Conditions: V_SSIO= V_SS= V_SSA= 0V, V_DDA= V_DDIO= 3.0–3.6V, V_DD= 2.25–2.75V, T_A= –40° to +85°C, C_L≤ 50pF, f_op= 80MHz

Characteristic

Timer input period

Symbol

P_IN

Min

4T+6

2T+3

2T

Max

—

Unit

ns

Timer input high/low period

Timer output period

P_INHL

P_OUT

—

ns

—

ns

Timer output high/low period

P_OUTHL

1T

—

ns

1. In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5ns.

2. Parameters listed are guaranteed by design.

56F826 Technical Data, Rev. 14

44

Freescale Semiconductor

Serial Communication Interface (SCI) Timing

Timer Inputs

P_IN

P_INHL

Timer Outputs

P_OUT

P_OUTHL

Figure 3-26 Quad Timer Timing

3.12 Serial Communication Interface (SCI) Timing

4

Table 3-16 SCI Timing

Operating Conditions: V_SSIO=V_SS= V_SSA= 0V, V_DDA=V_DDIO=3.0–3.6V, V_DD= 2.25–2.75V, T_A= –40° to +85°C, C_L≤ 50pF, f_op= 80MHz

Characteristic

Baud Rate¹

Symbol

BR

Min

—

Max

(f_MAX*2.5)/(80)

1.04/BR

Unit

Mbps

ns

RXD²Pulse Width

TXD³Pulse Width

RXD_PW

TXD_PW

0.965/BR

1.04/BR

ns

1. f_MAXis the frequency of operation of the system clock in MHz.

2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.

3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.

4. Parameters listed are guaranteed by design.

RXD

SCI receive

data pin

(Input)

RXD_PW

Figure 3-27 RXD Pulse Width

56F826 Technical Data, Rev. 14

Freescale Semiconductor

45

TXD

SCI receive

data pin

TXD_PW

(Input)

Figure 3-28 TXD Pulse Width

3.13 JTAG Timing

1, 3

Table 3-17 JTAG Timing

Operating Conditions: V_SSIO=V_SS= V_SSA= 0V, V_DDA=V_DDIO=3.0–3.6V, V_DD= 2.25–2.75V, T_A= –40° to +85°C, C_L≤ 50pF, f_op= 80MHz

Characteristic

TCK frequency of operation²

Symbol

Min

Max

Unit

f_OP

DC

10

MHz

TCK cycle time

t_CY

t_PW

t_DS

100

50

—

ns

TCK clock pulse width

TMS, TDI data set-up time

TMS, TDI data hold time

TCK low to TDO data valid

TCK low to TDO tri-state

TRST assertion time

DE assertion time

0.4

1.2

—

t_DH

—

t_DV

26.6

23.5

—

t_TS

—

t_TRST

t_DE

50

4T

—

1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz

operation, T = 12.5ns.

2. TCK frequency of operation must be less than 1/8 the processor rate.

3. Parameters listed are guaranteed by design.

t_CY

t_PW

V_IH

V_M

V_IL

V_M

TCK

(Input)

V_M= V_IL+ (V_IH– V_IL)/2

Figure 3-29 Test Clock Input Timing Diagram

56F826 Technical Data, Rev. 14

46

Freescale Semiconductor

JTAG Timing

TCK

(Input)

t_DS

t_DH

TDI

TMS

Input Data Valid

(Input)

t_DV

TDO

(Output)

Output Data Valid

t_TS

TDO

(Output)

t_DV

TDO

(Output)

Output Data Valid

Figure 3-30 Test Access Port Timing Diagram

TRST

(Input)

t_TRST

Figure 3-31 TRST Timing Diagram

DE

t_DE

Figure 3-32 OnCE—Debug Event

56F826 Technical Data, Rev. 14

Freescale Semiconductor

47

Part 4 Packaging

4.1 Package and Pin-Out Information 56F826

This section contains package and pin-out information for the 100-pin LQFP configuration of the 56F826.

GPIOD1

GPIOD0

GPIOB7

GPIOB6

GPIOB5

TMS

TDI

TDO

TRST

VDDIO

PIN 76

ORIENTATION

MARK

PIN 1

GPIOB4

GPIOB3

GPIOB2

VSSIO

A15

A14

GPIOB1

GPIOB0

A13

A12

CLKO

VDD

A11

A10

VSS

XTAL

A9

A8

EXTAL

VSSA

VDDA

VSSIO

A7

A6

A5

A4

VDDIO

STCK

VSS

VDD

STFS

STD

SRCK

SRFS

A3

A2

A1

A0

PIN 51

PIN 26

SRD

EXTBOOT

Figure 4-1 Top View, 56F826 100-pin LQFP Package

56F826 Technical Data, Rev. 14

48

Freescale Semiconductor

Package and Pin-Out Information 56F826

Table 4-1 56F826 Pin Identification by Pin Number

Signal

Name

Signal

Name

Pin No.

Signal Name

Pin No.

Signal Name

Pin No.

1

2

3

4

5

TMS

TDI

26

27

28

29

30

RD

WR

DS

51

52

53

54

55

SRD

SRFS

SRCK

STD

76

77

78

79

80

GPIOD2

GPIOD3

GPIOD4

GPIOD5

V_DDIO

TDO

TRST

V_DDIO

PS

V_DDIO

STFS

6

7

V_SSIO

A15

A14

A13

A12

31

32

33

34

35

V_SSIO

IRQA

IRQB

D0

56

57

58

59

60

STCK

V_DDIO

V_SSIO

V_DDA

V_SSA

81

82

83

84

85

V_SSIO

GPIOD6

GPIOD7

SCLK

8

9

10

D1

MOSI

11

12

13

A11

A10

A9

36

37

38

D2

D3

D4

61

62

63

EXTAL

XTAL

V_SS

86

87

88

MISO

SS

TA3

14

A8

39

D5

64

V_DD

89

TA2

15

16

17

18

19

A7

A6

40

41

42

43

44

D6

D7

65

66

67

68

69

CLKO

90

91

92

93

94

TA1

TA0

GPIOB0

GPIOB1

GPIOB2

GPIOB3

A5

D8

RXD1

TXD1

V_DD

A4

D9

V_SS

D10

20

V_DD

45

RESET

70

GPIOB4

95

V_SS

21

22

23

24

25

A3

A2

46

47

48

49

50

D11

D12

D13

D14

D15

71

72

73

74

75

GPIOB5

GPIOB6

GPIOB7

GPIOD0

GPIOD1

96

97

RXD0

TXD0

DE

A1

98

A0

99

TCS

TCK

EXTBOOT

100

56F826 Technical Data, Rev. 14

Freescale Semiconductor

49

S

0.15(0.006)

AC T-U

Z

-T-

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE -AB- IS LOCATED AT BOTTOM

OF LEAD AND IS COINCIDENT WITH THE

LEAD WHERE THE LEAD EXITS THE PLASTIC

BODY AT THE BOTTOM OF THE PARTING

LINE.

4. DATUMS-T-, -U-, AND-Z-TOBEDETERMINED

AT DATUM PLANE -AB-.

5. DIMENSIONS S AND V TO BE DETERMINED

AT SEATING PLANE -AC-.

-Z-

6. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION. ALLOWABLE

PROTRUSION IS 0.250 (0.010) PER SIDE.

DIMENSIONS A AND B DO INCLUDE MOLD

MISMATCH AND ARE DETERMINED AT

DATUM PLANE -AB-.

7. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION.DAMBARPROTRUSIONSHALL

NOT CAUSE THE D DIMENSION TO EXCEED

0.350 (0.014). DAMBAR CAN NOTBELOCATED

ON THE LOWER RADIUS OR THE FOOT.

MINIMUM SPACE BETWEEN PROTRUSION

AND AN ADJACENT LEAD IS 0.070 (0.003).

8. MINIMUM SOLDER PLATE THICKNESS

SHALL BE 0.0076 (0.003).

-U-

9. EXACT SHAPE OF EACH CORNER MAY VARY

FROM DEPICTION.

A

9

MILLIMETERS

DIM MIN MAX MIN MAX

INCHES

S

0.15(0.006)

AB T-U

Z

A

B

C

D

E

13.950 14.050 0.549 0.553

1.400 1.600 0.055 0.063

0.170 0.270 0.007 0.011

1.350 1.450 0.053 0.057

0.170 0.230 0.007 0.009

AE

AD

F

G

H

J

K

M

N

Q

R

S

0.500 BSC

0.020 BSC

-AB-

0.050 0.150 0.002 0.006

0.090 0.200 0.004 0.008

0.500 0.700 0.020 0.028

-AC-

SEATING

PLANE

G

96X

12 REF

°

(24X PER SIDE)

0.090 0.160 0.004 0.006

1

5

1

°

5

°

0.150 0.250 0.006 0.010

15.950 16.050 0.628 0.632

0.100(0.004) AC

V

W

X

0.200 REF

1.000 REF

0.008 REF

0.039 REF

°

M

R

D

F

0.25 (0.010)

E

C

GAUGE PLANE

J

N

W

°

Q

H

K

M

S

0.20(0.008)

AC T-U

Z

X

SECTION AE-AE

DETAIL AD

CASE 842F-01

Figure 4-2 100-pin LQPF Mechanical Information

Please see www.freescale.com for the most current case outline.

56F826 Technical Data, Rev. 14

50

Freescale Semiconductor

Thermal Design Considerations

Part 5 Design Considerations

5.1 Thermal Design Considerations

An estimation of the chip junction temperature, T , in °C can be obtained from the equation:

J

Equation 1:T_J= T_A+ (P_D× R_θJA

)

Where:

T_A= ambient temperature °C

R_θJA= package junction-to-ambient thermal resistance °C/W

P_D= power dissipation in package

Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and

a case-to-ambient thermal resistance:

Equation 2:R_θJA= R_θJC+ R_θCA

Where:

R_θJA= package junction-to-ambient thermal resistance °C/W

R_θJC= package junction-to-case thermal resistance °C/W

R_θCA= package case-to-ambient thermal resistance °C/W

R

is device-related and cannot be influenced by the user. The user controls the thermal environment to

θJC

change the case-to-ambient thermal resistance, R

. For example, the user can change the air flow around

θCA

the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or

otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This

model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through

the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where

the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the

device thermal performance may need the additional modeling capability of a system-level thermal

simulation tool.

The thermal performance of plastic packages is more dependent on the temperature of the PCB to which

the package is mounted. Again, if the estimations obtained from R

the thermal performance is adequate, a system-level model may be appropriate.

do not satisfactorily answer whether

θJA

Definitions:

A complicating factor is the existence of three common definitions for determining the junction-to-case

thermal resistance in plastic packages:

•

Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the

chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation

across the surface.

•

Measure the thermal resistance from the junction to where the leads are attached to the case. This definition

is approximately equal to a junction-to-board thermal resistance.

56F826 Technical Data, Rev. 14

Freescale Semiconductor

51

•

Use the value obtained by the equation (T_J– T_T)/P_D, where T_Tis the temperature of the package case

determined by a thermocouple.

The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T

thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so

that the thermocouple junction rests on the package. A small amount of epoxy is placed over the

thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire

is placed flat against the package case to avoid measurement errors caused by cooling effects of the

thermocouple wire.

When heat sink is used, the junction temperature is determined from a thermocouple inserted at the

interface between the case of the package and the interface material. A clearance slot or hole is normally

required in the heat sink. Minimizing the size of the clearance is important to minimize the change in

thermal performance caused by removing part of the thermal interface to the heat sink. Because of the

experimental difficulties with this technique, many engineers measure the heat sink temperature and then

back-calculate the case temperature using a separate measurement of the thermal resistance of the

interface. From this case temperature, the junction temperature is determined from the junction-to-case

thermal resistance.

5.2 Electrical Design Considerations

CAUTION

This device contains protective circuitry to guard

against damage due to high static voltage or

electrical fields. However, normal precautions are

advised to avoid application of any voltages higher

than maximum-rated voltages to this high-impedance

circuit. Reliability of operation is enhanced if unused

inputs are tied to an appropriate voltage level.

Use the following list of considerations to assure correct operation:

•

Provide a low-impedance path from the board power supply to each V_DD,V_DDIO,and V_DDApin on the

controller, and from the board ground to each V_SS,V_SSIO,and V_SSA(GND) pin.

•

The minimum bypass requirement is to place 0.1μF capacitors positioned as close as possible to the package

supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the

V_DD/V_SSpairs, including V_DDA/V_SSAand V_DDIO/V_SSIO.Ceramic and tantalum capacitors tend to provide

better performance tolerances.

•

Ensure that capacitor leads and associated printed circuit traces that connect to the chip V_DD,V_DDIO,and

V_DDAand V_SS,V_SSIO,and V_SSA(GND) pins are less than 0.5 inch per capacitor lead.

Bypass the V_DDand V_SSlayers of the PCB with approximately 100μF, preferably with a high-grade

capacitor such as a tantalum capacitor.

56F826 Technical Data, Rev. 14

52

Freescale Semiconductor

Electrical Design Considerations

•

Because the controller’s output signals have fast rise and fall times, PCB trace lengths should be minimal.

Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.

This is especially critical in systems with higher capacitive loads that could create higher transient currents

in the V_DDand V_SScircuits.

•

Take special care to minimize noise levels on the VREF, V_DDAand V_SSApins.

•

When using Wired-OR mode on the SPI or the IRQx pins, the user must provide an external pull-up device.

Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as development or

debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means

to assert TRST independently of RESET. TRST must be asserted at power up for proper operation. Designs

that do not require debugging functionality, such as consumer products, TRST should be tied low.

•

Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide an

interface to this port to allow in-circuit Flash programming.

56F826 Technical Data, Rev. 14

Freescale Semiconductor

53

Part 6 Ordering Information

Table 6-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor

sales office or authorized distributor to determine availability and to order parts.

Table 6-1 56F826 Ordering Information

Ambient

Frequency

(MHz)

Supply

Voltage

Count

Part

Package Type

Order Number

56F826

3.0–3.6 V

2.25-2.75 V

Plastic Quad Flat Pack (LQFP)

100

80

DSP56F826BU80

56F826

3.0–3.6 V

Plastic Quad Flat Pack (LQFP)

80

DSP56F826BU80E *

2.25-2.75 V

*This package is RoHS compliant.

56F826 Technical Data, Rev. 14

54

Freescale Semiconductor

Electrical Design Considerations

56F826 Technical Data, Rev. 14

Freescale Semiconductor

55

How to Reach Us:

Home Page:

www.freescale.com

E-mail:

support@freescale.com

USA/Europe or Locations Not Listed:

Freescale Semiconductor

Technical Information Center, CH370

1300 N. Alma School Road

Chandler, Arizona 85224

+1-800-521-6274 or +1-480-768-2130

support@freescale.com

Europe, Middle East, and Africa:

Freescale Halbleiter Deutschland GmbH

Technical Information Center

Schatzbogen 7

81829 Muenchen, Germany

+44 1296 380 456 (English)

+46 8 52200080 (English)

+49 89 92103 559 (German)

+33 1 69 35 48 48 (French)

support@freescale.com

RoHS-compliant and/or Pb-free versions of Freescale products have the

functionality and electrical characteristics of their non-RoHS-compliant

and/or non-Pb-free counterparts. For further information, see

http://www.freescale.com or contact your Freescale sales representative.

Japan:

Freescale Semiconductor Japan Ltd.

Headquarters

ARCO Tower 15F

For information on Freescale’s Environmental Products program, go to

http://www.freescale.com/epp.

1-8-1, Shimo-Meguro, Meguro-ku,

Tokyo 153-0064, Japan

0120 191014 or +81 3 5437 9125

support.japan@freescale.com

Information in this document is provided solely to enable system and

software implementers to use Freescale Semiconductor products. There are

no express or implied copyright licenses granted hereunder to design or

fabricate any integrated circuits or integrated circuits based on the

information in this document.

Asia/Pacific:

Freescale Semiconductor Hong Kong Ltd.

Technical Information Center

2 Dai King Street

Tai Po Industrial Estate

Tai Po, N.T., Hong Kong

+800 2666 8080

Freescale Semiconductor reserves the right to make changes without further

notice to any products herein. Freescale Semiconductor makes no warranty,

representation or guarantee regarding the suitability of its products for any

particular purpose, nor does Freescale Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation consequential or

incidental damages. “Typical” parameters that may be provided in Freescale

Semiconductor data sheets and/or specifications can and do vary in different

applications and actual performance may vary over time. All operating

parameters, including “Typicals”, must be validated for each customer

application by customer’s technical experts. Freescale Semiconductor does

not convey any license under its patent rights nor the rights of others.

Freescale Semiconductor products are not designed, intended, or authorized

for use as components in systems intended for surgical implant into the body,

or other applications intended to support or sustain life, or for any other

application in which the failure of the Freescale Semiconductor product could

create a situation where personal injury or death may occur. Should Buyer

purchase or use Freescale Semiconductor products for any such unintended

or unauthorized application, Buyer shall indemnify and hold Freescale

Semiconductor and its officers, employees, subsidiaries, affiliates, and

distributors harmless against all claims, costs, damages, and expenses, and

reasonable attorney fees arising out of, directly or indirectly, any claim of

personal injury or death associated with such unintended or unauthorized

use, even if such claim alleges that Freescale Semiconductor was negligent

regarding the design or manufacture of the part.

support.asia@freescale.com

For Literature Requests Only:

Freescale Semiconductor Literature Distribution Center

P.O. Box 5405

Denver, Colorado 80217

1-800-441-2447 or 303-675-2140

Fax: 303-675-2150

LDCForFreescaleSemiconductor@hibbertgroup.com

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor,

Inc. All other product or service names are the property of their respective owners.

This product incorporates SuperFlash® technology licensed from SST.

DSP56F826

Rev. 14

01/2007

型号：	56F826
PDF下载：	下载PDF文件查看货源
内容描述：	16位数字信号控制器 [16-bit Digital Signal Controllers]
分类和应用：	控制器
文件页数/大小：	56 页 / 987 K
品牌：	FREESCALE [ Freescale ]

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