Architecture Block Diagram
5
JTAG / EOnCE
Boot
Flash
pdb_m[15:0]
pab[20:0]
Program
Flash
Program
RAM
cdbw[13:0]
56800E
EMI
17
16
6
Address
CHIP
TAP
Controller
Data
Control
TAP
Linking
Module
Data
RAM
xab1[23:0]
xab2[23:0]
Data
Flash
External
JTAG
Port
cdbr_m[31:0]
xdb2_m[15:0]
To Flash
Control Logic
IPBus
Bridge
Flash
NOT available on the 56F8146 device.
Interface
Units
IPBus
Figure 1-1 System Bus Interfaces
Note:
Note:
Flash memories are encapsulated within the Flash Interface Unit (FIU). Flash control is accomplished
by the I/O to the FIU over the peripheral bus, while reads and writes are completed between the core
and the Flash memories.
The primary data RAM port is 32 bits wide. Other data ports are 16 bits.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
13
FREESCALE [ Freescale ]
